Analog Devices ADV8003 Hardware Manual page 8

8.4.19. SD Digital Noise Reduction .............................................................................................................................................. 339
8.4.19.1. Coring Gain Border ....................................................................................................................................................................... 340
8.4.19.2. Coring Gain Data ........................................................................................................................................................................... 340
8.4.19.3. DNR Threshold ............................................................................................................................................................................... 341
8.4.19.4. Border Area ..................................................................................................................................................................................... 341
8.4.19.5. Block Size Control .......................................................................................................................................................................... 342
8.4.19.6. DNR Input Select Control ............................................................................................................................................................. 342
8.4.19.7. DNR Mode Control ........................................................................................................................................................................ 342
8.4.19.8. DNR Block Offset Control ............................................................................................................................................................ 343
8.4.19.9. SD Active Video Edge Control...................................................................................................................................................... 343
8.5. Vertical Blanking Interval.............................................................................................................................................. 345
8.6. DAC Configurations ...................................................................................................................................................... 346
8.6.1. Voltage Reference ................................................................................................................................................................ 346
8.6.2. Video Output Buffer and Optional Output Filter .......................................................................................................... 346
9. Interrupts ................................................................................................................................................................. 349
9.1. Interrupt Pins .................................................................................................................................................................. 349
9.1.1. Interrupt Duration .............................................................................................................................................................. 349
9.1.2. Storing Masked Interrupts ................................................................................................................................................. 350
9.2. Serial Video Rx Interrupts ............................................................................................................................................. 350
9.2.1. Introduction ........................................................................................................................................................................ 350
9.2.2. Interrupt Architecture Overview ...................................................................................................................................... 354
9.2.2.1. Multiple Interrupt Events .................................................................................................................................................................... 355
9.2.3. Serial Video Interrupts Validity Checking Process ........................................................................................................ 355
9.3. VSP and OSD Section .................................................................................................................................................... 355
9.3.1. Interrupt Architecture Overview ...................................................................................................................................... 355
9.4. HDMI Tx core ................................................................................................................................................................. 356
9.4.1. Introduction ........................................................................................................................................................................ 356
9.4.2. Interrupt Architecture Overview ...................................................................................................................................... 356
9.4.3. HDMI Tx Interrupt Polarity.............................................................................................................................................. 357
Appendix A ........................................................................................................................................................................ 358
PCB Layout Recommendations.................................................................................................................................................... 358
Analogue/Digital Video Interface Outputs ...................................................................................................................................... 358
External DDR2 Memory Requirements ........................................................................................................................................... 358
Power Supply Bypassing ..................................................................................................................................................................... 359
General Digital Inputs and Outputs ................................................................................................................................................. 360
XTAL and Load Cap Value Selection ................................................................................................................................................ 360
Encoder Component Placement ....................................................................................................................................................... 361
HDMI Transmitter Component Placement ..................................................................................................................................... 361
Power Supply Design and Sequencing.............................................................................................................................................. 361
Appendix B ........................................................................................................................................................................ 363
ADV8003 Evaluation Board Schematics ..................................................................................................................................... 363
Appendix C ....................................................................................................................................................................... 393
ADV8003 Evaluation Board Layout ............................................................................................................................................ 394
Appendix D ....................................................................................................................................................................... 402
Package Outline Drawing .............................................................................................................................................................. 402
Appendix E ........................................................................................................................................................................ 403
Unused Pin List .............................................................................................................................................................................. 403
Rev. B, August 2013 8
ADV8003 Hardware Manual