Table 23: Pvsp Supported Output Video Timing And Vid - Analog Devices ADV8003 Hardware Manual

Note: The PVSP does not support the CEA-861 VIC 60 and CEA-861 VIC 61 formats.
pvsp_autocfg_output_vid[7:0], Primary VSP Map, Address 0xE882[7:0]
This register is used to set the output timing VIC. If this register is 0, PVSP will use values in registers of pvsp_dp_decount,
pvsp_dp_hfrontporch, pvsp_dp_hsynctime, pvsp_dp_hbackporch, pvsp_dp_activeline, pvsp_dp_vfrontporch, pvsp_dp_vsynctime,
pvsp_dp_vbackporch, pvsp_dp_hpolarity, pvsp_dp_vpolarity, pvsp_vout_fr and pvsp_dp_4kx2k_mode_en to set output video.
Function
pvsp_autocfg_output_v
id[7:0]
0x10 
0xXX
Table 23 lists the supported output video timings and the corresponding VID. 59.94/23.97 Hz timings have the same VID as the
corresponding 60/24 Hz timing in the table.
Rev. B, August 2013
Video Timing
480p240
480i240
VGA
SVGA
XGA
WXGA
VESA timing SXGA
WXGA-2
UXGA
WXGA-3
WUXGA
Description
Default: 1080p@60
Output timing VID

Table 23: PVSP Supported Output Video Timing and VID

Video Timing
640x480p60
720x480p60
720(1440)x240p60
720(2880)x240p60
1280x720p60
1920x1080p
720x576p50
1280x720p50
720x288p50
CEA 1920x1080p50
1920x1080p24
1920x1080p25
1920x1080p30
720p100
576p100
720p120
480p120
576p200
480p240
4kx2k 30 Hz
VID
56 or 57
58 or 59
200
201
202
203
204
205
206
207
208
VID
1
2 or 3 or 14 or 15 or 35 or 36
8 or 9
12 or 13
4
16
17 or 18 or 29 or 30 or 37 or 38
19
23 or 24 or 27 or 28
31
32
33
34
41
42 or 43
47
48 or 49
52 or 53
56 or 57
112
147
ADV8003 Hardware Manual