Page 1 ADV8005 Hardware Reference Manual UG-707 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com ADV8005 Functionality and Features PLEASE SEE THE LAST PAGE FOR AN IMPORTANT Rev. A | Page 1 of 317...
Page 2: Table Of Contents
UG-707 ADV8005 Hardware Reference Manual TABLE OF CONTENTS Understanding the ADV8005 Hardware Manual ......................10 Description of the Hardware Manual ............................10 Disclaimer ....................................... 10 Trademark and Service Mark Notice ............................10 Number Notations..................................10 Register Access Conventions ................................ 10 Acronyms and Abbreviations ...............................
Page 3 UG-707 2.1.14. Mode 13 – OSD from HDMI RX ............................. 40 2.1.15. Mode 14 – Handling Triple Inputs ........................... 41 2.2. ADV8005 Top Level Overview ............................. 41 2.2.1. Video Muxing ..................................41 2.2.2. Digital Video Input ................................45 2.2.2.1. Video TTL Input ....................................46 2.2.2.2.
Page 4 UG-707 ADV8005 Hardware Reference Manual 3.2.1.4. Field/Frame Buffer Address and Size ..............................108 3.2.1.5. Frame Latency ....................................... 110 3.2.1.6. Game Mode ......................................111 3.2.1.7. Low Latency Mode ....................................112 3.2.1.8. Freezing Output Video ..................................113 3.2.1.9. Progressive Cadence Detection ................................113 3.2.2.
Page 5 ADV8005 Hardware Reference Manual UG-707 3.4.1. Bootup Protocol .................................. 153 3.4.2. Reboot Protocol .................................. 154 3.4.3. Gentle Reboot Protocol ..............................155 3.4.4. VOM Set Protocol ................................156 3.4.5. Free Access Protocol ................................156 3.5. Horizontal Pre-scaler ..............................157 3.5.1. HPS Downscaling ................................158 3.5.2.
Page 6 UG-707 ADV8005 Hardware Reference Manual 5.9.4. SPD InfoFrame Registers ..............................190 5.9.5. MPEG Source InfoFrame Registers ..........................191 5.9.6. Vendor Specific InfoFrame Registers ..........................191 5.10. Packet Registers ................................192 5.10.1. ISRC Packet Registers ................................. 192 5.10.2. Gamut Metadata Packets ..............................194 5.11.
Page 7 Enabling and Disabling the HDMI TMDS Otuputs ....................240 6.17. HDMI TX Source Termination ............................ 241 6.18. HDMI ACR Packet Transmission ..........................242 Video Encoder Introduction to the ADV8005 ....................... 243 7.1. Introduction ..................................243 7.2. Input Configuration ............................... 243 7.3.
Page 8 UG-707 ADV8005 Hardware Reference Manual 7.4.19. SD Digital Noise Reduction .............................. 271 7.4.19.1. Coring Gain Border ..................................272 7.4.19.2. Coring Gain Data ................................... 272 7.4.19.3. DNR Threshold ....................................273 7.4.19.4. Border Area ..................................... 273 7.4.19.5. Block Size Control ..................................273 7.4.19.6.
Page 9 ADV8005 Hardware Reference Manual UG-707 REVISION HISTORY 1/15—Rev. 0 to Rev. A Changes to Spare Packets and VSI Support Section ....201 Added VSYNC Interrupt Section and Table 53; Renumbered Sequentially ................... 205 6/14—Revision 0: Initial Version Rev. A | Page 9 of 317...
Page 10: Understanding The Adv8005 Hardware Manual
The content of this document is believed to be correct. If any errors are found within this document or, if clarification is needed, contact Analog Devices. TRADEMARK AND SERVICE MARK NOTICE The Analog Devices logo is a registered trademark of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. NUMBER NOTATIONS...
Page 11 ADV8005 Hardware Reference Manual UG-707 Acronym/Abbreviation Description Ball Grid Array BKSV HDCP Receiver Key Selection Vector. Refer to HDCP documentation. Block Noise Reduction Consumer Electronics Control Component Processor Color Space Converter/Conversion CSync Composite Synchronization Cycle Time Stamp Color Upsampling Error...
Page 12 UG-707 ADV8005 Hardware Reference Manual Acronym/Abbreviation Description MPEG Moving Picture Expert Group Millisecond Most Significant Bit No Connect Noise Shaped Video On Screen Display One Time Programmable PtoI Progressive to Interlaced Pj’ HDCP Enhanced Link Verification Response. Refer to HDCP documentation.
Page 13: Field Function Description
ADV8005 Hardware Reference Manual UG-707 FIELD FUNCTION DESCRIPTION The function of a field is described in a table preceded by the bit name, a short function description, the I C map, the register location within the I C map, and a detailed description of the field. Refer to Figure 1 for more details.
Page 14: References
UG-707 ADV8005 Hardware Reference Manual REFERENCES HDMI Licensing and LLC, High-Definition Multimedia Interface, Revision 1.4a, March 4, 2010 Digital Content Protection (DCP) LLC, High-bandwidth Digital Content Protection System, Revision 1.3, December 21, 2006 CEA, CEA-861-E, A DTV Profile for Uncompressed High Speed Digital Interfaces, Revision E, September 11, 2007 ITU, ITU-R BT.656-4, Interface for Digital Component Video Signals in 525-Line and 625-Line Television Systems Operating at the 4:2:2 Level...
Page 15: Introduction To The Adv8005
3D depth to OSD displays. This allows customers to create advanced OSD designs to differentiate their products. Once created, OSD designs are stored in an external SPI flash memory connected to the ADV8005. The control of the OSD must be performed from the system microcontroller via SPI.
Page 16: Digital Video Input
ADV8005 or a serial video link between the ADV7623 the ADV8005. Using such front end devices located before the ADV8005 allows the audio to be extracted and processed in a DSP before being reinserted into the ADV8005. A mux after the TTL inputs allows the video TTL input pins and the EXOSD TTL input pins to be connected to either the primary or the secondary input channel.
Page 17: Flexible Digital Core
ADV8005 Hardware Reference Manual UG-707 ADV8 0 0 5 Secondary I N P U T D I T H E R Input F M T + C S C Channel EXOSD 148.5MHz to H i g h S p e e d...
Page 18: Bitmap On Screen Display
UG-707 ADV8005 Hardware Reference Manual ADV8005 can downscale from 4k x 2k to 1080p. The PVSP can be employed to further scale the downscaled 4k x 2k content. When using the PVSP as the primary scaler, the SVSP can also be used to provide a second lower resolution output format. The PVSP and SVSP can be connected in parallel or in series.
Page 19: External Ddr2 Memory
ADV8005 Hardware Reference Manual UG-707 1.1.5. External DDR2 Memory DDR2 Interface DDR2 Interface Motion Motion Frame Rate Frame Rate Bitmap OSD Bitmap OSD Adaptive Adaptive Conversion Conversion Data Data De-interlacer De-interlacer Figure 5: External DDR2 Memory Interface External DDR2 memory is required for motion adaptive de-interlacing, Frame Rate Conversion (FRC), and OSD bitmap overlay.
Page 20: Main Features Of The Adv8005
UG-707 ADV8005 Hardware Reference Manual 1.2. MAIN FEATURES OF THE ADV8005 1.2.1. Video Signal Processor 1.2.1.1. Primary VSP • 12-bit internal processing • Fixed frame latency capability • Input timing up to 1080p • Output timing up to 4k x 2k •...
Page 21: Video Encoder
ADV8005 Hardware Reference Manual UG-707 1.2.3. Video Encoder • Six NSV 12-bit video DACs • Compliant with all common SMPTE formats • Multiformat video output support NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support Composite (CVBS) and S-Video (Y/C) component/YPrPb/RGB (SD, ED and HD) •...
Page 22 UG-707 ADV8005 Hardware Reference Manual DDR2 CONTROLLER INTERF ACE AUDIO DATA CAPTURE DDR2 INTERFACE DDC1_SC L HDCP AND EDID DDC1_SD A MICRO- MASTER DDC2_SC L CONTROLLER RX_0 P DDC2_SD A RX_0N RX_1 P AUTO- HPD_TX1 POSITION RX_1N HPD_TX2 HDCP HDCP...
Page 23: Protocol For Main I 2 C Port
C writes needed are 0x1A, 0x59, 0xAF, 0xFF. The addresses are outlined in Table Figure 7 shows the register map architecture for the ADV8005. Table 2: ADV8005 C Address and Register Address Range for Different HW Blocks Register Map Name...
Page 24: Configuring The Adv8005
UG-707 ADV8005 Hardware Reference Manual Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, these cause an immediate jump to the idle condition. During a given SCLK high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition.
Page 25: Adv8005 Top Level Control
OSD can be blended before the PVSP to display the OSD on all outputs, the OSD can be blended before the output to display the OSD on a single output. This has been divided into several modes of operation which are recommended by Analog Devices. These modes of operation are documented in Section and outline the most practical modes in which to configure the ADV8005.
Page 26: Adv8005 Modes Of Operation
UG-707 ADV8005 Hardware Reference Manual 2.1. ADV8005 MODES OF OPERATION This section outlines the most practical modes in which the ADV8005 can be configured, as recommended by ADI. These modes describe the various ways to configure the VSP block, depending on the input formats as well as the outputs required.
Page 27: Selecting A Mode
There are limitations to both of these methods. Rendering OSDs at larger resolutions increases the system resources required to store these bitmaps. Alternatively, scaling the OSD internally in the part increases power consumption on the ADV8005. The optimum solution to this depends on customer requirements and system capabilities. It should be chosen taking these considerations into account.
Page 28: Mode 1
UG-707 ADV8005 Hardware Reference Manual 2.1.2. Mode 1 Mode 1 should be used if: • Three separate output formats are required • Additional processing (BNR, RNR, and so on) is required on the new output formats • OSD is required on a single output format (most likely the lowest quality of the converted formats)
Page 29: Mode 2
ADV8005 Hardware Reference Manual UG-707 2.1.3. Mode 2 Mode 2 should be used if: • Three separate output formats are required • Additional processing (BNR, RNR, and so on) is required on the new output formats • OSD is required on multiple outputs •...
Page 30: Mode 3
UG-707 ADV8005 Hardware Reference Manual 2.1.4. Mode 3 Mode 3 should be used if: • Two separate upscaled resolutions are required • De-interlacing is not required • OSD is required on one resolution only (preferably the higher resolution output) Mode 3...
Page 31: Mode 4
ADV8005 Hardware Reference Manual UG-707 2.1.5. Mode 4 Mode 4 should be used if: • Three possible separate output formats are required • Additional processing is required on the new output formats • OSD is required on multiple output formats...
Page 32: Mode 5
UG-707 ADV8005 Hardware Reference Manual 2.1.6. Mode 5 Mode 5 should be used if: • Two separate upscaled resolutions are required • De-interlacing is not required • OSD is required on both output formats Mode 5 Mode 5 OSD rendered at a single set resolution: 720p...
Page 33: Mode 6
ADV8005 Hardware Reference Manual UG-707 2.1.7. Mode 6 Mode 6 should be used if: • Two separate upscaled resolutions are required • De-interlacing is not required • OSD is required on one resolution only (preferably the lower upscaled resolution output)
Page 34: Mode 7
UG-707 ADV8005 Hardware Reference Manual 2.1.8. Mode 7 Mode 7 should be used if: • HDMI input video is copy protected • Additional processing is required on the new output formats • OSD is required on multiple outputs • OSD and video scaling are to be kept separate...
Page 35: Mode 8
ADV8005 Hardware Reference Manual UG-707 2.1.9. Mode 8 Mode 8 should be used if: • HDMI input video is copy protected • Additional processing is required on the new output formats • OSD is required on multiple outputs • OSD and video scaling are to be kept separate...
Page 36: Mode 9 - Bypass
UG-707 ADV8005 Hardware Reference Manual 2.1.10. Mode 9 - Bypass Mode 9 should be used if input video is to be passed straight to the output with no video processing. Mode 9 - Bypass Mode 9 - Bypass DDR2 Memory...
Page 37: Mode 10 - Picture In Picture (Pip) (External Osd Less Than 720P)
ADV8005 Hardware Reference Manual UG-707 2.1.11. Mode 10 – Picture in Picture (PiP) (External OSD Less Than 720p) Mode 10 should be used if: • OSD data is input via the EXOSD TTL 24-bit input port • OSD data input via the EXOSD TTL 24-bit input port is less than 720p Mode 10 - PiP (External OSD <...
Page 38: Mode 11 - Pip (External Osd Greater Than Or Equal To 720P)
UG-707 ADV8005 Hardware Reference Manual 2.1.12. Mode 11 – PIP (External OSD Greater Than or Equal To 720p) Mode 11 should be used if: • OSD data is input via the EXOSD TTL 24-bit input port • OSD data input via the EXOSD TTL 24-bit input port is greater than or equal to 720p Mode 11 is used to support the external input of either part of or the complete OSD from another device, for example, an MCU.
Page 39: Mode 12 - Dual Zone Osd
ADV8005 Hardware Reference Manual UG-707 2.1.13. Mode 12 – Dual Zone OSD Mode 12 should be used if OSD output is required in dual zones. Mode 12 - PiP (External OSD < 720p) Mode 12 - PiP (External OSD < 720p)
Page 40: Mode 13 - Osd From Hdmi Rx
UG-707 ADV8005 Hardware Reference Manual 2.1.14. Mode 13 – OSD from HDMI RX Mode 13 should be used if the ADV8005 is being used in conjunction with a legacy standalone OSD generator with an HDMI interface. Mode 13 Mode 13...
Page 41: Mode 14 - Handling Triple Inputs
ADV8005 Hardware Reference Manual UG-707 2.1.15. Mode 14 – Handling Triple Inputs Mode 14 should be used if three independent video streams are required on the output of the ADV8005. Mode 14 Mode 14 DDR2 Memory DDR2 Memory Interface Interface...
Page 42 _ e n c _ i n p _ s e l [ 3 : 0 ] External Secondary Input Channel RX Input Channel s_inp_chan_sel[1] ADV8005 Figure 25: ADV8005 Digital Core Muxing The following registers are used to configure the video routed through the ADV8005. Rev. A | Page 42 of 317...
Page 43 ADV8005 Hardware Reference Manual UG-707 tx1_inp_sel[3:0], IO Map, Address 0x1A03[7:4] This signal is used to select the video source for the HDMI Tx1. Function tx1_inp_sel[3:0] Description 0x00 (default) From Primary Input Channel 0x01 From Primary VSP 0x02 From PtoI Converter...
Page 44 UG-707 ADV8005 Hardware Reference Manual svsp_inp_sel[3:0], IO Map, Address 0x1A05[7:4] This signal is used to select the video source for the Secondary VSP. Function svsp_inp_sel[3:0] Description 0x00 (default) From Primary Input Channel 0x01 From Internal OSD Blend 1 0x02 From Primary VSP...
Page 45: Digital Video Input
ADV8005 Hardware Reference Manual UG-707 For example, when using the ADV8005 in Mode 3 (described in Section 2.1.4), the following register settings are needed to configure the video data path: 1A 1A03 34; Output of OSD blend to HDMI Tx1, Output of Secondary VSP to HDMI Tx2 1A 1A04 30;...
Page 46: Video Ttl Input
UG-707 ADV8005 Hardware Reference Manual 2.2.2.1. Video TTL Input The video TTL input pins are defined as follows: • P[47:0] • • • • PCLK The video TTL input pins can be connected to either the primary input channel (refer to Section 2.2.2.6) or the secondary input channel (refer to Section 2.2.2.7).
Page 47 ADV8005 Hardware Reference Manual UG-707 Figure 29: TTL Output Block Diagram The following registers are used to control the TTL outputs. ttl_ps444_in, IO Map, Address 0x1A01[0] This bit is used to select the video type sent to the TTL output format block.
Page 48: Treatment O F Unused Ttl Inputs
UG-707 ADV8005 Hardware Reference Manual ttl_out_sel[2:0], IO Map, Address 0x1A02[2:0] This signal is used to select the video source for the TTL video output. Function ttl_out_sel[2:0] Description 0x00 (default) From Primary Input Channel 0x01 From Primary VSP 0x02 From PtoI Converter...
Page 49 ADV8005 Hardware Reference Manual UG-707 osd_pins_ie[23:0], IO Map, Address 0x1BCD[7:0]; Address 0x1BCE[7:0]; Address 0x1BCF[7:0] This bit is used to control the input path enable for the osd pins. Function osd_pins_ie[23:0] Description 0 (default) input path disable input path enable hs_ie, IO Map, Address 0x1BD0[7] This bit is used to control the input path enable for the HS pin.
Page 50 UG-707 ADV8005 Hardware Reference Manual arc1_pin_ie, IO Map, Address 0x1BD2[7] This bit is used to control the input path enable for the ARC 1 pin. Function arc1_pin_ie Description 0 (default) input path disable input path enable arc2_pin_ie, IO Map, Address 0x1BD2[6] This bit is used to control the input path enable for the ARC 2 pin.
Page 51 ADV8005 Hardware Reference Manual UG-707 spi1_mosi_ie, IO Map, Address 0x1BD3[5] This bit is used to control the input path enable for the spi1 MOSI pin. Function spi1_mosi_ie Description 0 (default) input path disable input path enable spi1_sclk_ie, IO Map, Address 0x1BD3[4] This bit is used to control the input path enable for the spi1 SCLK pin.
Page 52: Serial Video Rx
UG-707 ADV8005 Hardware Reference Manual mas_vs_ie, IO Map, Address 0x1BD4[0] This bit is used to control the input path enable for the master VS pin. Function mas_vs_ie Description 0 (default) input path disable input path enable 2.2.2.5. Serial Video Rx...
Page 53 ADV8005 Hardware Reference Manual UG-707 vid_swap_bus_ctrl[2:0], IO Map, Address 0x1B48[7:5] This signal is used to control the video input pixel bus. The input pixel bus is 36 bits wide and is divided into three data channels: Top = D[35:24], Middle = D[23:12] and Bottom = D[11:0]. This register allows the user to swap the order of these three data channels.
Page 54 UG-707 ADV8005 Hardware Reference Manual if video input to the device is not in this format, this must be first converted to 4:4:4. Setting this bit to 1 converts video data to 4:4:4. vid_ps444_r444_conv, IO Map, Address 0x1B49[6] This bit is used to convert 4:2:2 data to pseudo 444 or to real 444.
Page 55 ADV8005 Hardware Reference Manual UG-707 vid_av_pos_sel, IO Map, Address 0x1B4B[3] This bit is used to select if the HS generated is consistent with EIA 861 timing or dependant on the embedded timing codes. Function vid_av_pos_sel Description 0 (default) Generate HS coincident with EAV code...
Page 56 UG-707 ADV8005 Hardware Reference Manual brightness[7:0] value has a range of -1024 to 1016. Refer to Figure 32 for more information on how the brightness controls influence the video signal. saturation[7:0] value has a range 0 to 1.992. Refer to...
Page 57: Secondary Input Channel
ADV8005 Hardware Reference Manual UG-707 blank_level_u[11:0], IO Map, Address 0x1A26[7:0]; Address 0x1A27[7:4] This signal is used to adjust the blank level of u input to the vid adjust block. Function blank_level_u[11:0] Description 0x000 u blank level sits at code 0...
Page 58 UG-707 ADV8005 Hardware Reference Manual exosd_format_sel[4:0], IO Map, Address 0x1B68[4:0] This signal is used to select the input format for the video data. Function exosd_format_sel[4:0] Description 0x00 1 x 8 bit bus 4:2:2 0x01 1 x 10 bit bus 4:2:2...
Page 59 ADV8005 Hardware Reference Manual UG-707 exosd_ddr_edge_sel, IO Map, Address 0x1B6A[3] This bit is used to select which edge the first sample of DDR data is latched on. Function exosd_ddr_edge_sel Description 0 (default) Posedge data first Negedge data first Using the pixel clock as a reference, ADV8005 expects the Y sample on a rising edge and then a chroma sample on the falling edge.
Page 60 UG-707 ADV8005 Hardware Reference Manual exosd_de_pol, IO Map, Address 0x1B69[2] This bit is used to set the polarity of the input External OSD DE timing signal. Function exosd_de_pol Description 0 (default) Input DE polarity doesn’t change. Input DE polarity gets inverted.
Page 61: Rx Input Channel
ADV8005 Hardware Reference Manual UG-707 exosd_ud_bypass_man_en, IO Map, Address 0x1B6A[2] This bit is used to enable the manual bypass for the up dither. Setting this bit enables the bypass to be used. Function exosd_ud_bypass_man_en Description 0 (default) Manual bypass disable...
Page 62: Updither Configuration
UG-707 ADV8005 Hardware Reference Manual 2.2.3. Updither Configuration The updither block on each of the input channels can be used to increase the bit width of the incoming video. This is useful if the output video must be a certain bit depth and the input video is below this level. Updither can increase color richness and reduce the effects of quantization, rounding and truncation which may have been induced on the video data.
Page 63 ADV8005 Hardware Reference Manual UG-707 OSD_IN[35] Secondary OSD_IN[0] OSD_VS Inputs OSD_HS OSD_DE Set by exosd_in_id P[35] P[35] Main P[0] P[0] Inputs Set by vid_in_id Rx2+ Rx2+ Rx2- Rx2- Serial Rx1+ Rx1+ Rx1- Rx1- Video Rx0+ Rx0+ Rx0- Rx0- RxC+ RxC+...
Page 64 UG-707 ADV8005 Hardware Reference Manual video_in_id[7:0], IO Map, Address 0x1A00[7:0] This register is used to set the output clock frequencies from the input video formatting block used by both the Serial Video RX and Video TTL input ports. Function video_in_id[7:0]...
Page 65 ADV8005 Hardware Reference Manual UG-707 exosd_in_id[7:0], IO Map, Address 0x1B6C[7:0] This register is used to specify the video_id relative to CEA 861. Function exosd_in_id[7:0] Description 0x01 CEA 861 VIC 1 (480p_60 640) 0x02 CEA 861 VIC 2 (480p_60) 0x03 CEA 861 VIC 3 (480p_60)
Page 66: Pvsp Output Timing
Depending on the sampling frequency required, the following registers need to be programmed with this DPLL clock period. Note: To enable the DPLL to configure the correct clocks for the ADV8005, register 0x0039 must be set to 0x0A. This register must always be configured before the following registers are set.
Page 67: Svsp Output Timing
ADV8005 Hardware Reference Manual UG-707 pvsp_vid_clk_update, IO Map, Address 0x1A3A[4] This bit is used to trigger the open loop period to be captured in the DPLL. A low to high transition triggers the action. Function pvsp_vid_clk_update Description 0 (default) Do not update open_loop_period in DPLL...
Page 68: Ddr2 Interface
UG-707 ADV8005 Hardware Reference Manual from 1080p30 to 720p59.94 with frame tracking enabled, the resulting output may be 720p60 due to the 1:2 relationship. Frame rate tracking is primarily intended for cases where the input frame rate and output frame rate have a 1:1 relationship or are close to this target, that is, 59.94 Hz to 60 Hz.
Page 69: Ddr2 Configuration
For example, if using 256 Mb memory, sdram_size[3:0] should be set to 0001. If using 2 Gb memory, sdram_size[3:0] should be set to 0100. word_size[3:0] burst_length[2:0] fields must also be configured depending on whether there are single or multiple memories connected to the ADV8005. If there is a single DDR2 memory, word_size[3:0] burst_length[2:0] should be set for a 32-bit word size and bursts of 8.
Page 70: Ddr2 Bandwidth And Memory Selection
UG-707 ADV8005 Hardware Reference Manual Figure 38: DDR2 PLL Architecture Figure 38 shows the block diagram of the PLL with the relevant I C controls. The formula used to determine the frequency of the DDR2 memory interface clock is given in...
Page 71 ADV8005 Hardware Reference Manual UG-707 Table 7: Indication of ADV8005 Capabilities with Two DDR2 Memories Features Motion Random Noise Dual Output (ADV8005- Adaptive De- Reduction 8A/8N/8C only) interlacing SD input Supported Supported Supported Total area of all OSD Supported regions (on screen at same...
Page 72: Single Ddr2 Memory Configuration
UG-707 ADV8005 Hardware Reference Manual 2.2.5.3. Single DDR2 Memory Configuration If using a single DDR2 memory, the number of field buffers must be reduced from seven (default) to four when performing de-interlacing and scaling on 720p, 1080i and 1080p inputs. This is achieved by enabling intra field interpolation and setting (pvsp_ex_mem_data_format[1:0]) to indicate 16-bit 4:2:2.
Page 73: I 2 C Auto Increment
ADV8005. By default, this is set to 1 which means that a read from a particular address in the...
Page 74: Spi Loop Through
UG-707 ADV8005 Hardware Reference Manual 2.2.7. SPI Loop Through ADV8005 SPI ports can be put in loop through mode for programming the external SPI flash that may be connected to the ADV8005 master SPI port (if an OSD design is to be used). Refer to Section 4.2.8...
Page 75: Spi Data Extraction
ADV8005 Hardware Reference Manual UG-707 format of the ancillary data packet is shown in Table Table 9: Output Mode Outline Byte Description Ancillary Data Preamble DID Data Identification Word I2C_DID6[4:0] SDID Secondary Data Identification I2C_SDID7_2[5:0] Word ID1 User Data Word 1...
Page 76: Resets
Resets This section documents the register bits used for resetting various sections of the ADV8005. These resets can be used by the system controller to reset individual sections of the device without having to reset the whole part. If the whole device needs to be reset, this can be implemented by setting the global reset, main_reset.
Page 77 ADV8005 Hardware Reference Manual UG-707 pvsp_reset, IO Map, Address 0x1AFD[6] (Self-Clearing) This bit is used to reset the Primary VSP. Function pvsp_reset Description 0 (default) Default Reset p2i_reset, IO Map, Address 0x1AFD[5] (Self-Clearing) This bit is used to reset the Progressive to Interlaced core.
Page 78: Image Processing Colorimetry Breakdown
UG-707 ADV8005 Hardware Reference Manual enc_reset, IO Map, Address 0x1AFE[6] (Self-Clearing) This bit is used to reset the HD and SD encoders. Function enc_reset Description 0 (default) Default Reset tx2_reset, IO Map, Address 0x1AFE[5] (Self-Clearing) This bit is used to reset the HDMI TX2.
Page 79: Av-Codes
AV-Codes Embedded end of active video (EAV) and start of active video (SAV) timing codes are supported on the TTL inputs of the ADV8005. AV-code information is embedded into the pixel data and is transmitted using a standard 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace.
Page 80 UG-707 ADV8005 Hardware Reference Manual • UXGA (1600x1200) • WXGA(1366x768 • WUXGA (1900x1200) A number of CEA formats are not supported automatically for AV-codes 1920x1080p @ 23.97/24 Hz (CEA VIC 32) 1920x1080p @ 25 Hz (CEA VIC 33) 1920x1080p @ 29.97/30 Hz (CEA VIC 34) 1280x720p @ 23.97/24 Hz (CEA VIC 60)
Page 81 ADV8005 Hardware Reference Manual UG-707 vs_h_beg_e_pos[10:0], IO Map, Address 0x1B93[7:0]; Address 0x1B94[7:5] This signal is used to specify the horizontal beginning position of VS for even fields (counting from the EAV), if CEA 861 timing generation is enable and manual values selected.
Page 82 UG-707 ADV8005 Hardware Reference Manual Function hs_end_pos[9:0] Description 0xXX release hs when hcount reaches 0xXX vs_h_beg_o_pos[10:0], IO Map, Address 0x1B91[2:0]; Address 0x1B92[7:0] This signal is used to specify the horizontal beginning position of VS for odd fields (counting from the EAV), if CEA 861 timing generation is enable and manual values selected.
Page 83: Color Space Conversion
ADV8005 Hardware Reference Manual UG-707 de_h_beg_pos (276) hs_end_pos (38 + 124 = 162) hs_beg_pos (38) vs_h_beg_o_pos (38) vs_h_beg_e_pos (38) de_v_beg_e_pos (22) vs_v_beg_pos (4) vs_v_end_pos (7) de_v_beg_o_pos (22) vs_v_beg_pos (4) vs_v_end_pos (7) Figure 42: 720(1440) x 240p @ 59.94/60Hz, CEA Formats 8 and 9 2.2.12.
Page 84 UG-707 ADV8005 Hardware Reference Manual vid_csc_enable, IO Map, Address 0x1B30[7] This bit is used to control the Primary Input Channel CSC. Function vid_csc_enable Description 0 (default) CSC disable CSC enable vid_csc_mode[1:0], IO Map, Address 0x1B30[6:5] This signal is used to specify the CSC mode for the Primary Input Channel CSC. The CSC mode sets the fixed point position of the CSC coefficients, including a4, b4, c4 and offsets.
Page 85 ADV8005 Hardware Reference Manual UG-707 Table 10: Default Primary Input Channel CSC Signal Routing Input Channel Default RGB Routing Default YCbCr Routing In_A In_B In_C The A1 to A3, B1 to B3, and C1 to C3 coefficients are used to scale the primary inputs. A4, B4 and C4 are added as offsets. Floating point coefficients must be converted into 120-bit fixed decimal format then converted into binary format using twos complement for negative values and can only be programmed in the range [-1….+1] or [-4096….+4095].
Page 86: Secondary Input Channel Csc
UG-707 ADV8005 Hardware Reference Manual Color Space Conversion RGB (limited) 0x0 0x082E 0x1893 0x1F3F 0x0800 0x0367 0x0B71 0x0128 0x0000 0x1E21 0x19B2 0x082D 0x0800 to HDTV YCbCr (limited) RGB (limited) 0x0 0x082E 0x1926 0x1EAC 0x0800 0x04C9 0x0965 0x01D2 0x0000 0x1D3F 0x1A93 0x082E 0x0800...
Page 87 ADV8005 Hardware Reference Manual UG-707 The characteristic equations for the secondary input CSC are provided in Equation Equation 8 Equation   ∗ ∗ ∗ ∗ scale     4096 4096 4096 Equation 7: Secondary Input CSC Channel A Output ...
Page 88 UG-707 ADV8005 Hardware Reference Manual The CSC configurations for common modes are provided in Table Table 13: Secondary Input Channel CSC Common Configuration Coefficients Color Space Conversion HDTV YCbCr 0x1 0x0C53 0x0800 0x0000 0x19D6 0x1C56 0x0800 0x1E88 0x0291 0x1FFF 0x0800 0x0E85 0x18BE...
Page 89: Rx Input Channel Csc
ADV8005 Hardware Reference Manual UG-707 Color Space Conversion RGB (limited) Identity Matrix 0x1 0x0800 0x0000 0x0000 0x0000 0x0000 0x0800 0x0000 0x0000 0x0000 0x0000 0x0800 0x0000 (Output = Input) 2.2.12.3. RX Input Channel CSC The CSC must be manually configured for each color space conversion. The CSC on the RX input channel can be enabled using the rx_csc_enable control.
Page 90 UG-707 ADV8005 Hardware Reference Manual rx_csc_mode 4096 rx_a4 rx_a1 Out_A ÷ In_A rx_a2 In_B rx_a3 In_C Figure 45: RX Input Channel CSC The video inputs In_A, In_B and In_C are connected by default to R, G and B. For more information, please see Table 14.
Page 91 ADV8005 Hardware Reference Manual UG-707 Table 15: RX Input Channel CSC Common Configuration Coefficients Color Space Conversion HDTV YCbCr 0x1 0x0C53 0x0800 0x0000 0x19D6 0x1C56 0x0800 0x1E88 0x0291 0x1FFF 0x0800 0x0E85 0x18BE (limited) to RGB (limited) HDTV YCbCr 0x2 0x0734...
Page 92: Ttl Output Csc
UG-707 ADV8005 Hardware Reference Manual 2.2.12.4. TTL Output CSC Models of ADV8005 which provide TTL output now have a CSC in that path, allowing, for example, theTTL output video to be converted to RGB. The TTL output CSC has the same structure as the primary input CSC but it is limited to a maximum pixel clock frequency of 162MHz.
Page 93 ADV8005 Hardware Reference Manual UG-707 ttl_out_a4[12:0], IO Map, Address 0x1BB6[4:0]; Address 0x1BB7[7:0] This signal is used to specify the ttl out channel CSC coefficient A4. ttl_out_b1[12:0], IO Map, Address 0x1BB8[4:0]; Address 0x1BB9[7:0] This signal is used to specify the ttl out channel CSC coefficient B1.
Page 94 UG-707 ADV8005 Hardware Reference Manual Table 16 TTL Output Channel CSC Common Configuration Coefficients Color Space Conversion HDTV YCbCr 0x1 0x0C53 0x0800 0x0000 0x19D6 0x1C56 0x0800 0x1E88 0x0291 0x1FFF 0x0800 0x0E85 0x18BE (limited) to RGB (limited) HDTV YCbCr 0x2 0x0734...
Page 95: Hdmi Transmitter Cscs
ADV8005 Hardware Reference Manual UG-707 2.2.12.5. HDMI Transmitter CSCs Both of the HDMI transmitters feature an any-to-any CSC. The CSC register controls for HDMI Tx1 are described here; the same controls co- exist in the HDMI Tx2 Main Map for the HDMI Tx2 CSC.
Page 96 UG-707 ADV8005 Hardware Reference Manual csc_scaling_factor 4096 csc_a4 csc_a1 Out_A ÷ In_A csc_a2 In_B csc_a3 In_C Figure 47: HDMI Tx CSC The video inputs In_A, In_B and In_C are connected by default to R, G and B. Refer to Table 17 for more information.
Page 97 ADV8005 Hardware Reference Manual UG-707 Table 18: HDMI Tx CSC Common Configuration Coefficients Color Space Conversion HDTV YCbCr 0x1 0x0C53 0x0800 0x0000 0x19D6 0x1C56 0x0800 0x1E88 0x0291 0x1FFF 0x0800 0x0E85 0x18BE (limited) to RGB (limited) HDTV YCbCr 0x2 0x0734 0x04AD 0x0000 0x1C1B 0x1DDC 0x04AD 0x1F24 0x0135 0x0000 0x04AD 0x087C 0x1B77...
Page 98: Vga Position And Phase Information
UG-707 ADV8005 Hardware Reference Manual 2.2.13. VGA Position and Phase Information ADV8005 can measure picture position and sample quality information and record these in on-chip registers. This information can be read and used by the software on an external MCU to program the optimum sampling clock frequency and phase for an external Video AFE when it is sampling a VGA-type input signal.
Page 99 ADV8005 Hardware Reference Manual UG-707 CSC input used for Set the number Enable auto Select TTL/RX input auto phase of phases phase IO map - 0x1BE0[5] IO map - 0x1BE0[7:6] IO map - 0x1BE1 [6:0] IO map - 0x1BE1[7] Reset auto phase...
Page 100 UG-707 ADV8005 Hardware Reference Manual Figure 51: Graphics Video Timing Parameters Similar to the autophase, the auto position block is designed to tune the ADC sampling clock frequency in a device with an analog front end. To carry it out, the block will analyse the graphics input and return the top, bottom, left and right pixel vacancy numbers. This information, along with the input standard format, can then be used to adjust the ADC sampling clock frequency.
Page 101 ADV8005 Hardware Reference Manual UG-707 ADV7850 ADV7850 VFE map - 0x16,0x17 CP map -0x8C,0x8D Set front end pll ratio Increase fend horizontal Set fend datapath and Detect video standard first, blanking area AVI to RGB then enable manual pll Set ADV8005 datapath...
Page 102 UG-707 ADV8005 Hardware Reference Manual auto_ph_en, IO Map, Address 0x1BE1[7] This bit is used to enable auto phase detection block Function auto_ph_en Description 0 (default) Disabled Enabled auto_ph_num[6:0], IO Map, Address 0x1BE1[6:0] This control signal sets the total number of phases available on the front end part, e.g. 8, 16, 32, etc auto_ph_scan[5:0], IO Map, Address 0x1BE2[5:0] This control signal sets the scan phase number being tested.
Page 103: Adv8005 Silicon Revision
0 (default) Rovi Enabled Rovi Disabled 2.2.15. System Configuration When configuring a system featuring an HDMI Rx and ADV8005, the following sequences for HDMI Tx and encoder are recommended. For HDMI Tx: Configure the HDMI Rx (ADV7850). Wait until the ADV8005 Serial Video Rx achieves lock.
Page 104: Video Signal Processing
PVSP, SVSP, and the PtoI converter. These hardware blocks are completely independent of each other and can be placed in various configurations within the ADV8005. Access to an external DDR2 memory can be required for the PVSP and SVSP to operate correctly. The PVSP needs access to external DDR2 memory in every mode except game mode.
Page 105: Autoconfiguration
ADV8005 Hardware Reference Manual UG-707 pvsp_bypass, Primary VSP Map, Address 0xE829[7] This bit is used to bypass the Primary VSP. If this bit is set to 1, the input video to the Primary VSP will be directly bypassed to the output port.
Page 106 UG-707 ADV8005 Hardware Reference Manual Table 19: PVSP Supported Input Video Timing and VID Video Timing 640x480p60 720x480p60 2 or 3 or 14 or 15 or 35 or 36 720x240p60 8 or 9 or 12 or 13 1280x720p60 1920x1080i60 720x480i60...
Page 107: Customized Input/Output Video Format Configuration
ADV8005 Hardware Reference Manual UG-707 60/24 Hz timing in the table. Table 20: PVSP Supported Output Video Timing and VID Video Timing 640x480p60 720x480p60 2 or 3 or 14 or 15 or 35 or 36 720(1440)x240p60 8 or 9 720(2880)x240p60...
Page 108: Field/Frame Buffer Number
UG-707 ADV8005 Hardware Reference Manual pvsp_vin_h[10:0], Primary VSP Map, Address 0xE82E[2:0]; Address 0xE82F[7:0] This signal is used to set the horizontal resolution of the input video. This register's value will be used while pvsp_man_input_res is 1 or pvsp_autocfg_input_vid is 0.
Page 109 ADV8005 Hardware Reference Manual UG-707 The value programmed into each of these registers is determined by Equation × active video width active video height ≡ field size xbytes pixel PVSP_IS_I_ TO_P Equation 19: Calculating External Memory Field Buffers where: •...
Page 110: Frame Latency
UG-707 ADV8005 Hardware Reference Manual pvsp_fieldbuffer4_addr[31:0], Primary VSP Map, Address 0xE810[7:0]; Address 0xE811[7:0]; Address 0xE812[7:0]; Address 0xE813[7:0] This signal is used to set the start address of field/frame buffer 4. Software should arrange memory space properly, avoiding conflict between different buffers.
Page 111: Game Mode
ADV8005 Hardware Reference Manual UG-707 When crop or album mode is enabled, frame latency will be different from what is listed in Table 21. In this case, the user can use the following methods to measure frame latency: pvsp_rb_frame_latency[2:0] pvsp_rb_hsync_latency[11:0] are read only registers. Their values are real-time frame and HSync latency between input and output video.
Page 112: Low Latency Mode
UG-707 ADV8005 Hardware Reference Manual pvsp_bypass_ddr_mode, Primary VSP Map, Address 0xE84D[5] This bit is used to enable game mode for the Primary VSP. Function pvsp_bypass_ddr_mode Description 0 (default) Normal mode Game mode External memory is not used in game mode. Intra-field interpolation is used for interlaced input. Mosquito/block noise reduction and sharpness are supported in game mode, both for interlaced input and progressive input.
Page 113: Freezing Output Video
ADV8005 Hardware Reference Manual UG-707 The following functions are not supported In low latency mode: • Motion adaptive de-interlacing (autodisabled) • Cadence detection (autodisabled) • Random noise reduction (autodisabled) • CUE correction (autodisabled) pvsp_frc_low_latency_mode, Primary VSP Map, Address 0xE84D[2] This bit is used to enable low latency mode.
Page 114: Pvsp Video Input Module
UG-707 ADV8005 Hardware Reference Manual 3.2.2. PVSP Video Input Module Video Input Module (VIM) Video Input Module (VIM) Input Input Horizontal Horizontal Video Video Cropper Cropper Down Scaler Down Scaler Pixel Pixel Packer Packer Write to Write to DDR2 DDR2 Figure 55: PVSP Video Input Module 3.2.2.1.
Page 115 ADV8005 Hardware Reference Manual UG-707 pvsp_vim_crop_h_start[10:0], Primary VSP Map, Address 0xE832[2:0]; Address 0xE833[7:0] This signal is used to set the horizontal start position of the VIM cropper. Function pvsp_vim_crop_h_start[10:0] Description 0x000 (default) Default 0xXXX Horizontal start position of VIM cropper input pvsp_vim_crop_v_start[10:0], Primary VSP Map, Address 0xE834[2:0];...
Page 116: Horizontal Down Scaler
UG-707 ADV8005 Hardware Reference Manual 3.2.2.2. Horizontal Down Scaler Although the VOM has both horizontal and vertical scalers, there is also a horizontal down scaler in the VIM. The purpose of the VIM down scaler is to save external memory bandwidth by doing horizontal downscaling before writing video data into the external memory to save memory bandwidth.
Page 117: Scaler Controls
ADV8005 Hardware Reference Manual UG-707 pvsp_vim_scal_type[1:0], Primary VSP Map, Address 0xE8E5[7:6] This signal is used to set the VIM scaling algorithm. For up-scaling, the proprietary ADI algorithm is recommended; whereas for down- scaling, the sharp setting is recommended. Function pvsp_vim_scal_type[1:0]...
Page 118: Pvsp Video Output Module
Scaler: scales video to target resolution • Output port: generates output timing and output video Register update protection is provided in the ADV8005. Refer to Section for more details regarding how to update the various VSP registers. pvsp_lock_vom, Primary VSP Map, Address 0xE828[3] This bit is used to lock the Video Output Module (VOM).
Page 119: Pixel Unpacker
ADV8005 Hardware Reference Manual UG-707 pvsp_update_vom, Primary VSP Map, Address 0xE828[4] This bit is used to control the updating of the VOM. Registers in the VOM can be updated only when pvsp_update_vom is asserted. To modify registers in the VOM, pvsp_update_vom should be de-asserted. The registers can then be modified. pvsp_update_vom should then be asserted to let the VOM use the updated register value in the next frame.
Page 120: Motion Detection
UG-707 ADV8005 Hardware Reference Manual pvsp_di_crop_h_start[10:0], Primary VSP Map, Address 0xE83C[2:0]; Address 0xE83D[7:0] This signal is used to set the horizontal start position of the VOM cropper. Function pvsp_di_crop_h_start[10:0] Description 0x000 (default) Default 0xXXX Horizontal start position of VOM cropper input pvsp_di_crop_v_start[10:0], Primary VSP Map, Address 0xE83E[2:0];...
Page 121: Low Angle De-Interlacing
ADV8005 Hardware Reference Manual UG-707 pvsp_motionbuf0_addr[31:0], Primary VSP Map, Address 0xE818[7:0]; Address 0xE819[7:0]; Address 0xE81A[7:0]; Address 0xE81B[7:0] This signal is used to set the start address of motion information buffer 0. Motion buffers are needed only when motion adaptive deinterlacing is enabled for interlaced input.
Page 122: Cue Correction
UG-707 ADV8005 Hardware Reference Manual The PVSP supports the following cadence types: • • 2:2:2:4 • • 2:3:3:2:2 • 2:3:3:2 • 3:2:3:2:2 • • • • • Each of these cadence types can be disabled by setting the corresponding bit in di_fd_disabled_cadence[10:0] to 1.
Page 123: Random Noise Reduction
ADV8005 Hardware Reference Manual UG-707 di_cue_enable, Primary VSP Map, Address 0xE84D[0] This bit is used to enable CUE correction. Function di_cue_enable Description Disable CUE correction 1 (default) Enable CUE correction 3.2.3.7. Random Noise Reduction There are several noise reduction algorithms in the ADV8005 that help with the reduction of common sources of video noise.
Page 124: Mosquito Noise Reduction
UG-707 ADV8005 Hardware Reference Manual pvsp_rnrbuf1_addr[31:0], Primary VSP Map, Address 0xE824[7:0]; Address 0xE825[7:0]; Address 0xE826[7:0]; Address 0xE827[7:0] Sets the start address of random noise reduction information buffer 1. RNR buffers are needed only when random noise reduction is enabled. Function...
Page 125 ADV8005 Hardware Reference Manual UG-707 Table 25: Corresponding Value for Block Noise Reduction Level Register Name High Middle di_bnr_detect_scale_line[3:0] di_bnr_disable_local_detect di_bnr_edge_offset[7:0] di_bnr_global_strength_gain[3:0] di_bnr_scale_global_hori[2:0] di_bnr_scale_global_vert[2:0] di_bnr_enable, Primary VSP Map, Address 0xE84C[6] This bit is used to enable block noise reduction (BNR).
Page 126: Sharpness Enhancement
UG-707 ADV8005 Hardware Reference Manual di_bnr_detect_scale_line[3:0], Primary VSP 2 Map, Address 0xE987[7:4] This signal is used to configure the BNR processing ability. Function di_bnr_detect_scale_line[3:0] Description 0111 (default) Recommended setting for low/mid level BNR 1001 Recommended setting for high level BNR 3.2.3.10.
Page 127 ADV8005 Hardware Reference Manual UG-707 pvsp_srscal_interp_mode[1:0], Primary VSP Map, Address 0xE894[7:6] This signal is used to select the scaler algorithm employed. Function pvsp_srscal_interp_mode[1:0 Description 00 (default) Automatic scaler algorithm selection Contour-based interpolation scaler (2nd gen scaling algorithm with 4k x 2k support)
Page 128: Panorama Mode
Table 26 for the register settings for the common CEA video formats that are supported by the ADV8005. The output setting can be automatically configured using the setting of pvsp_autocfg_output_vid[7:0]. If the output configuration needs to be set manually, pvsp_man_dp_timing_enable...
Page 129 ADV8005 Hardware Reference Manual UG-707 pvsp_dp_4kx2k_mode_en, Primary VSP Map, Address 0xE869[4] This bit is used to make the VOM display module work in 4K x 2K mode. This register's value will be used while pvsp_autocfg_output_vid is 0. Function pvsp_dp_4kx2k_mode_en Description...
Page 130 UG-707 ADV8005 Hardware Reference Manual pvsp_dp_vfrontporch[9:0], Primary VSP Map, Address 0xE860[1:0]; Address 0xE861[7:0] This signal is used to set the vertical front porch duration of output timing. This register's value will be used while pvsp_autocfg_output_vid is 0. Function pvsp_dp_vfrontporch[9:0] Description...
Page 131: Demo Function
Not output default color Output default Color 3.2.3.14. Demo Function ADV8005 supports automatically splitting the display window to demo several processing functions of ADV8005. pvsp_demo_window_enable can be used to enable the demo function. pvsp_demo_window_enable, Primary VSP Map, Address 0xE87E[7] Enables demo window.
Page 132 UG-707 ADV8005 Hardware Reference Manual pvsp_demo_window_use_lower_screen can be used to set the position of the demo window. If this bit is set to 1, the lower half display window is used for certain processing function, otherwise the upper half display window is used.
Page 133: Progressive To Interlaced Converter
ADV8005 Hardware Reference Manual UG-707 pvsp_demo_window_cue_enable, Primary VSP Map, Address 0xE87F[5] This bit is used to enable CUE correction in the demo window. Function pvsp_demo_window_cue_en Description able 0 (default) Disable CUE in demo window Enable CUE in demo window' pvsp_demo_window_intra_field_enable, Primary VSP Map, Address 0xE87F[4] This bit is used to enable the intra field interpolation in the demo window.
Page 134: Automatic Contrast Enhancement
UG-707 ADV8005 Hardware Reference Manual Table 27: VID Set to PtoI Input Timing Format to 576p 1080p50 480p 1080p60 svsp_m_p2i_vid The PVSP PtoI does not have direct access to the data from the input pins but it can be utilized to convert a progressive input format to interlaced...
Page 135 ADV8005 Hardware Reference Manual UG-707 VOM of the SVSP. In the SVSP only, the VIM is capable of scaling video data. This means that the VIM of the SVSP can support vertical resolution scaling as well as horizontal resolution scaling.
Page 136: Autoconfiguration
UG-707 ADV8005 Hardware Reference Manual 3.3.1.1. Autoconfiguration Each block inside the VIM and the VOM can be automatically configured to decrease the configuration complexity. The svsp_autocfg_input_vid[7:0] svsp_autocfg_output_vid[7:0] registers should be set to make the autoconfiguration work. The 59.94/23.97 Hz timings have the same VID as the corresponding 60/24 Hz timing in...
Page 137 ADV8005 Hardware Reference Manual UG-707 svsp_autocfg_output_vid[7:0], Secondary VSP Map, Address 0xE661[7:0] This register is used to set the output timing VIC. If this register is 0, SVSP will use values in registers of svsp_dp_decount, svsp_dp_hfrontporch, svsp_dp_hsynctime, svsp_dp_hbackporch, svsp_dp_activeline, svsp_dp_vfrontporch, svsp_dp_vsynctime, svsp_dp_vbackporch, svsp_dp_hpolarity, svsp_dp_vpolarity and svsp_vout_fr to set output video.
Page 138: Customized Input/Output Video Format Configuration
UG-707 ADV8005 Hardware Reference Manual 3.3.1.2. Customized Input/Output Video Format Configuration If the input timing is not in the SVSP input format table, the input format needs to be set manually. If the input resolution has a variation in regard to standard timing (for example, if...
Page 139 ADV8005 Hardware Reference Manual UG-707 For example, for an output video resolution of 720p, Equation 22 would yield the following field size: Field_size = ((1280)x(720))x2 = 1843200 where no_bytes_per_pixel indicates the number of bytes required to store each pixel. Refer to...
Page 140: Frame Latency
UG-707 ADV8005 Hardware Reference Manual svsp_fieldbuffer6_addr[31:0], Secondary VSP Map, Address 0xE66C[7:0]; Address 0xE66D[7:0]; Address 0xE66E[7:0]; Address 0xE66F[7:0] This signal is used to set the start address of field/frame buffer 6. Software should arrange memory space properly, avoiding conflict between different buffers.'...
Page 141: Freezing Output Video
ADV8005 Hardware Reference Manual UG-707 svsp_frc_latency_measure_en, Secondary VSP Map, Address 0xE662[2] This bit is used to enable measuring frame/Hsync latency. Function svsp_frc_latency_measure_e Description 0 (default) Disable Enable svsp_rb_frame_latency[2:0], Secondary VSP Map, Address 0xE6F2[7:5] (Read Only) This signal is used to readback the realtime frame latency.
Page 142: Vim Cropper
UG-707 ADV8005 Hardware Reference Manual 3.3.2.1. VIM Cropper The VIM cropper block is used to define a sub window within the given input resolution. This cropped image will then become the video which will be processed by the SVSP. The following registers are used to define this sub window.
Page 143: Scaler
ADV8005 Hardware Reference Manual UG-707 svsp_vim_crop_width[12:0], Secondary VSP Map, Address 0xE61E[7:0]; Address 0xE61F[7:3] This signal is used to set the input width of the VIM cropper. Function svsp_vim_crop_width[12:0] Description 0x000 (default) Default 0xXXX Width of VIM cropper input svsp_vim_crop_height[12:0], Secondary VSP Map, Address 0xE620[7:0]; Address 0xE621[7:3] This signal is used to set the input height of the VIM cropper.
Page 144: Scaler Interpolation Mode
UG-707 ADV8005 Hardware Reference Manual Image before Image before Scaler in Scaler in Scaled Image Scaled Image Scaler Scaler VSP2D_VIM_SCAL_OUT_HEIGHT SVSP_VIM_SCAL_OUT_HEIGHT VSP2D_VIM_CROP_HEIGHT SVSP_VIM_CROP_HEIGHT SVSP_VIM_CROP_WIDTH SVSP_VIM_SCAL_OUT_WIDTH Figure 65: VIM Scaler Dimensions 3.3.2.3. Scaler Interpolation Mode This section describes the method for scaling the input video data. The purpose of the scaler is to allow different input formats to be displayed on a screen with a fixed resolution.
Page 145: Panorama Mode
ADV8005 Hardware Reference Manual UG-707 svsp_man_scaler_para_enable, Secondary VSP Map, Address 0xE662[4] This bit is used to enable manually setting scaler parameters. Function svsp_man_scaler_para_enabl Description 0 (default) Disable Enable When a picture is zoomed in, it is possible to maintain the original high frequency content. However, maintaining this content can sometimes introduce ringing artifacts.
Page 146: Svsp Video Output Module
VOM cropper: reads cropped images from external memory • Output port: generates output timing and output video Register update protection is provided in the ADV8005. Refer to Section for more details regarding the update of the various VSP registers. svsp_lock_vom, Secondary VSP Map, Address 0xE610[4] 'This bit is used to lock the Video Output Module (VOM).
Page 147: Pixel Unpacker
ADV8005 Hardware Reference Manual UG-707 3.3.3.1. Pixel Unpacker The pixel unpacker in the VOM of the SVSP is similar to that in the VOM of the PVSP. The pixel unpacker is used to convert external memory words (128 bits) into video pixel (YCbCr-8-8-8-bit) data. Pixels in external memory can have the following two different data formats which are the same as those set by the VIM.
Page 148: Output Port
UG-707 ADV8005 Hardware Reference Manual svsp_vom_crop_v_start[10:0], Secondary VSP Map, Address 0xE628[7:0]; Address 0xE629[7:5] This signal is used to set the vertical start position of the VOM cropper. Function svsp_vom_crop_v_start[10:0] Description 0x000 (default) Default 0xXXX Vertical start position of VOM cropper svsp_vom_crop_width[10:0], Secondary VSP Map, Address 0xE62A[7:0];...
Page 149 ADV8005 Hardware Reference Manual UG-707 svsp_dp_hfrontporch[11:0], Secondary VSP Map, Address 0xE634[7:0]; Address 0xE635[7:4] This signal is used to set the horizontal front porch duration of output timing. This register's value will be used while svsp_autocfg_output_vid is 0. Function svsp_dp_hfrontporch[11:0] Description...
Page 150 UG-707 ADV8005 Hardware Reference Manual svsp_dp_vpolarity, Secondary VSP Map, Address 0xE642[7] This signal is used to set the polarity of output Vsync. This register's value will be used while svsp_autocfg_output_vid is 0. Function svsp_dp_vpolarity Description 0 (default) High svsp_dp_hpolarity, Secondary VSP Map, Address 0xE642[6] This signal is used to set the polarity of output Hsync.
Page 151: Ddr Bypass Mode
ADV8005 Hardware Reference Manual UG-707 svsp_dp_video_h_start[10:0], Secondary VSP Map, Address 0xE62E[7:0]; Address 0xE62F[7:5] This signal is used to set the horizontal start position where the output video of scaler is placed. Function svsp_dp_video_h_start[10:0] Description 0x000 (default) Default 0xXXX Horizontal start position of output port svsp_dp_video_v_start[10:0], Secondary VSP Map, Address 0xE630[7:0];...
Page 152: Progressive To Interlaced Converter In Svsp
UG-707 ADV8005 Hardware Reference Manual 3.3.3.5. Progressive to Interlaced Converter in SVSP The PtoI converter block in the SVSP is used to convert progressive video to interlaced video. It drops odd or even lines of the progressive video based on the output interlaced video field signal. Support is limited to 480p and 576p. The associated interlaced timing signals can be generated in the PtoI hardware block.
Page 153: Bootup Protocol
ADV8005 Hardware Reference Manual UG-707 3.4.1. Bootup Protocol The bootup protocol is used to configure the PVSP or SVSP from a reset state. All registers can be accessed using this protocol. Figure 69: Bootup Protocol Flowchart Figure 69 shows the process for the bootup protocol for the PVSP. This is exactly the same for the SVSP with the appropriate registers replaced.
Page 154: Reboot Protocol
UG-707 ADV8005 Hardware Reference Manual 3.4.2. Reboot Protocol The reboot protocol is used to reset the PVSP and configure it again using different settings, especially different input timing or output timing. All registers can be accessed using this protocol. It should be noted that the output video will be interrupted using this protocol.
Page 155: Gentle Reboot Protocol
ADV8005 Hardware Reference Manual UG-707 3.4.3. Gentle Reboot Protocol The gentle reboot is used to reboot the PVSP with different configuration settings but does not interrupt the output timing. The output video is frozen during this protocol. All registers except output video timing registers can be accessed.
Page 156: Vom Set Protocol
UG-707 ADV8005 Hardware Reference Manual 3.4.4. VOM Set Protocol The VOM set protocol is used to configure the VOM. The registers in the VOM can be accessed without affecting the output video timing. Figure 72: VOM Set Protocol Flowchart Figure 72 shows the process for the VOM set protocol for the PVSP.
Page 157: Horizontal Pre-Scaler
A Horizontal Pre-Scaler (HPS) has been implemented on the ADV8005 to extend the scaling functions of the ADV8005. The PVSP and SVSP are limited in the pixel clock frequencies and line lengths which they can handle. The HPS block has been designed for scaling between determined video formats as follows: Down-conversion of video standards with pixel clocks greater than 162MHz and/or more than 2048 pixels/line.
Page 158: Hps Downscaling
UG-707 ADV8005 Hardware Reference Manual hps_power_down. hps_power_down, IO Map, Address 0x1A85[7] Powers down the horizontal pre-scaler block (HPS). Powered down by default to save power Function hps_power_down Description HPS is active 1 (default) HPS Block is powered down hps_filt_bypass, IO Map, Address 0x1A85[4] This bit bypasses filtering done before downsampling.
Page 159: Hps Upscaling
ADV8005 Hardware Reference Manual UG-707 Figure 75 HPS effect of hps_phase_sel_downsample In order to perform downscaling of video standards with pixel clocks greater than 162MHz, it will be necessary to go through the HPS before routing the video to either the PVSP or SVSP.
Page 160: Using The Hps For Converting Between 3D To 2D Video Formats
UG-707 ADV8005 Hardware Reference Manual Format Int/Pr Field Pixel H Freq Rate Freq [kHz] Freq tota acti tota acti blan [Hz] [MHz] [Hz] [dot [line [dot [dot [dot [line [line [line [dot [dot [line [line 1920x10 59.94/6 134.8 59.9 1920x10 112.5...
Page 161: Side By Side Full
ADV8005 Hardware Reference Manual UG-707 The following formats are not supported Format Int/Pr Field Rate tota acti total acti blan [Hz] [dot [line [line [dot [dot [dot [line [line [dot [dot [line [line 1920x10 Prog 119,88/ 1920x10 Prog 3.5.4. 3D Side by Side Full The following 3D standards need to go through the HPS before being converted to a 2D mode.
Page 162: Side By Side Full
UG-707 ADV8005 Hardware Reference Manual The following standards are NOT supported. Format Int/Pr Field Rate tota acti total acti blan [Hz] [dot [line [line [dot [dot [dot [line [line [dot [dot [line [line 1920x10 Prog 119,88/ 1920x10 Prog 3.5.5. 3D Side by Side Full The following 3D standards need to go through the HPS before being converted to a 2D mode.
Page 163: Functional Description
It is important to note that if the output timing is being locked to the external MAS_VS reference it cannot be locked to the input timing at the same time. This means that if there are frequency differences between the external timing and input timing provided to the ADV8005, input frames of video will be either dropped or repeated to account for these differences and keep the output timing locked to the external master reference (MAS_VS).
Page 164 Applications where the ADV8005/ADV8003 output is required to be locked to the input timing do not require this functionality. These applications (e.g. video wall) can use ‘phase locked frame track mode’ to achieve this functionality. The output will be locked within +/- 2xtal clocks after an initial lock time of 0 –...
Page 165: Progressive To Interlaced Conversion
ADV8005 Hardware Reference Manual UG-707 svsp_track_offset[20:0], IO Map, Address 0x1A97[4:0]; Address 0x1A98[7:0]; Address 0x1A99[7:0] This signal is used to program the delay on the output timing of vsyncs from the Secondary VSP. Function svsp_track_offset[20:0] Description 0 (default) input and output vsync coincident 1 xltal clk between input nad output vsync 3.7.
Page 166: On Screen Display
UG-707 ADV8005 Hardware Reference Manual 4. ON SCREEN DISPLAY 4.1. INTRODUCTION The On Screen Display (OSD) core in the ADV8005 allows the user to overlay a bitmap-based OSD onto one of the input video streams. The OSD blend is capable of being performed at data rates up to 3 GHz. The OSD can be designed using the ADI Blimp software tool. This code generating tool may be used to design, simulate and compile the OSD which will be used in the end system application.
Page 167: Typical Osd Component Sizes
ADV8005 Hardware Reference Manual UG-707 DDR2 DDR2 Microcontroller Microcontroller SPI Flash SPI Flash Memory Memory Slave Master Slave Master Video Input 1 Video Input 1 Blended Output 1 Blended Output 1 Blend Blend ADV8002 Output 1 Input 1 ADV8003 Video Input 2...
Page 168: Osd Blending
UG-707 ADV8005 Hardware Reference Manual DDR2 DDR2 Memory Memory OSD TTL Input External Core SPI Master/ SPI Master/ Microcontroller/ Microcontroller/ Slave Slave Core Core Flash Flash Internally Generated Core Scaler Scaler Video Input 1 Video Input 1 Blended Output 1...
Page 169: External Alpha Blending
The OSD core generates the internal data for the OSD display. It accesses the DDR2 memory (through a DMA controller) to load the required resources. reg_osd_enable is used to enable the OSD core on the ADV8005. reg_osd_enable, OSD, Address 0xEE00[0] The enable bit of OSD core.
Page 170: Osd Core Region Definition
UG-707 ADV8005 Hardware Reference Manual 4.2.5.1. OSD Core Region Definition A region defines an area on the plane, as shown in Figure 84. The regions are derived from the OSD components defined in the Blimp OSD software and, therefore, contain the different elements of the OSD, for example, the text, images, icons, and so on. In other words, the regions define how the OSD pixels to be displayed are stored in DDR2 memory.
Page 171: Osd Color Space
ADV8005 Hardware Reference Manual UG-707 4.2.5.2. OSD Color Space Bitmap images as well as external OSDs are passed to the OSD core in 8-bit RGB format. However, all video processing in the ADV8005 takes place in YCbCr. The OSD core features a CSC to enable conversion of the OSD data from RGB to YCbCr. The OSD core CSC can convert into either full of limited range YCbCr.
Page 172 UG-707 ADV8005 Hardware Reference Manual timer1_reset, SPI Device Address 0x0B (TIMER), Address 0x04[0] Timer 1 Reset Function timer1_reset Description 0  Not reset Reset Enabling this reset will clear the timer_cnt and timer_irq_cnt registers. Note that the rest of the bits within this register perform the same operation as for timer1 but for the other seven timers (that is, bit[1] controls timer2, bit[2] controls timer3, and so on);...
Page 173 ADV8005 Hardware Reference Manual UG-707 timer1_flag, SPI Device Address 0x0B (TIMER), Address 0x09[0] (Read Only) Timer 1 flag. Function timer1_flag Description 0  Timer 1 is running Timer 1 is done Note that the rest of the bits within this register perform the same operation as for timer1 but for the other seven timers (that is, bit[1] controls timer2, bit[2] controls timer3, and so on);...
Page 174: Osd Scaler
OSD requires an external DDR2 memory and some configuration done to the OSD SPI registers in order to work. OSD data can be written to the DDR2 memory on startup by the ADV8005. In addition, to dynamically configure the OSD, configuration registers need to be controlled.
Page 175 ADV8005 Hardware Reference Manual UG-707 Config Register OSD_CORE Master Slave Slave FLASH System DDR2 Memory Controller(CPU) Figure 87: MCU as SPI Master Sending OSD Data Through ADV8005 SPI Slave Interface Additionally, the system MCU (SPI master) can program the external flash by looping SPI commands through the SPI slave (serial port 1) and the SPI master (serial port 2) interfaces connected in a chain.
Page 176 UG-707 ADV8005 Hardware Reference Manual Config Register OSD_CORE Master Slave Slave FLASH System DDR2 Memory Controller(CPU) Figure 88: SPI Loopback Enabled so MCU Can Program SPI Flash By default, the SPI ports are set in manual mode for the SPI which means the SPI pins are tristated (input). To make the SPI ports operational, the following register bits must be configured to automatic mode.
Page 177 ADV8005 Hardware Reference Manual UG-707 spi2_cs_oe_man_en, IO Map, Address 0x1ACE[3] This bit is used to control the output enable manual override for spi2_cs. Function spi2_cs_oe_man_en Description Auto 1 (default) Manual override spi2_miso_oe_man_en, IO Map, Address 0x1ACE[2] This bit is used to control the output enable manual override for spi2_miso.
Page 178: Spi Slave Interface
SPI slave interface (serial port 1) is used by the MCU to send the OSD data to the DDR2 and to configure the OSD registers. Note that the SPI functions provided within the ADI libraries will automatically take care of any SPI transfer between the MCU and ADV8005.
Page 179 ADV8005 Hardware Reference Manual UG-707 CPOL CPHA SCK1 SCK1 SCK1 SCK1 Device Address Data in 0 Data in 1 Sub Address MOSI1 Dummy byte Data out 0 Delay Mode MISO1 Data out 0 Data out 1 No Delay Mode MISO1...
Page 180: Spi Master Interface
UG-707 ADV8005 Hardware Reference Manual spi_filter_en, IO Map, Address 0x1A2C[7] This bit is used to enable the SPI anti glitch filter. Function spi_filter_en Description 0 (default) Anti glitch filter disable Anti glitch filter enable spi_filter_sel, IO Map, Address 0x1A2C[6] This bit is used to select the response of the SPI anti glitch filter.
Page 181: Osd Initialization
ADV8005 Hardware Reference Manual UG-707 The CPOL/CPHA can be configured through the following I C registers. spi_master_cpol, IO Map, Address 0x1A14[1] This bit is used to select the SPI master clock polarity. Function spi_master_cpol Description 0 (default) Idle state, clock is low...
Page 182: Serial Video Receiver
UG-707 ADV8005 Hardware Reference Manual 5. SERIAL VIDEO RECEIVER The Serial Video Rx on the ADV8005 can receive video data at rates of up to 3 GHz. This allows support for video formats ranging from SD to 4k x 2k @ 24Hz, 1080p120Hz and 1080p60 3D. The Serial Video Rx on the ADV8005 can receive video data at rates of up to 2.25 GHz.
Page 183: Tmds Clock Activity Detection
ADV8005 Hardware Reference Manual UG-707 dis_cable_det_rst, HDMI RX Map, Address 0xE248[6] This bit is used to disable the reset effects of cable detection. It should be set to 1 if the +5 V pins are unused and left unconnected. Function...
Page 184: Av Mute Status
UG-707 ADV8005 Hardware Reference Manual 5.4. AV MUTE STATUS av_mute is used to indicate the status of the avmute bit in the general control packet. As with the TMDS clock detection bits, this register bit can be polled by the system software and the appropriate configuration done.
Page 185: Video Fifo
ADV8005 Hardware Reference Manual UG-707 5.6. VIDEO FIFO ADV8005 contains a FIFO located after the TMDS decoding block (refer to Figure 92). Data arriving into the Serial Video Rx will be at 1X rate for non deep color modes (8-bits per channel), and 1.25X, 1.5X, or 2X for deep color modes (30, 36 and 48 bits respectively). Data unpacking...
Page 186: Pixel Repetition
UG-707 ADV8005 Hardware Reference Manual dcfifo_kill_dis, HDMI RX Map, Address 0xE21B[2] This bit is used to control whether or not the Video FIFO output is zeroed if there is more than one resynchronization of the pointers within 2 FIFO cycles. This behavior can be disabled with this bit.
Page 187: Sync Signal Polarity Readbacks
ADV8005 Hardware Reference Manual UG-707 derep_n[3:0], HDMI RX Map, Address 0xE241[3:0] This signal is used to set the derepetition value if derep_n_override is set to 1. Function derep_n[3:0] Description 0000 (default) DEREP_N+1 indicates the pixel and clock discard factor xxxx DEREP_N+1 indicates the pixel and clock discard factor 5.8.
Page 188: Infoframe Registers
UG-707 ADV8005 Hardware Reference Manual Data Enable HSYNC VSYNC Total number of lines in field 0. Unit is in half lines. Actives number of lines in field 0. Unit is in lines. VSync front porch width in field 0. Unit is in half lines.
Page 189: Avi Infoframe Registers
ADV8005 Hardware Reference Manual UG-707 5.9.3. AVI InfoFrame Registers Table 35 provides a list of readback registers for the AVI InfoFrame data. Refer to the EIA/CEA-861 specifications for a detailed explanation of the AVI InfoFrame fields. Table 35: AVI InfoFrame Registers...
Page 190: Spd Infoframe Registers
UG-707 ADV8005 Hardware Reference Manual 5.9.4. SPD InfoFrame Registers Table 36 provides a list of readback registers available for the SPD InfoFrame. Refer to the EIA/CEA-861 specifications for a detailed explanation of the SPD InfoFrame fields. Table 36: SPD InfoFrame Registers...
Page 191: Mpeg Source Infoframe Registers
ADV8005 Hardware Reference Manual UG-707 5.9.5. MPEG Source InfoFrame Registers Table 37 provides a list of readback registers available for the MPEG InfoFrame. Refer to the EIA/CEA-861 specifications for a detailed explanation of the MPEG InfoFrame fields. Table 37: MPEG InfoFrame Registers...
Page 192: Packet Registers
UG-707 ADV8005 Hardware Reference Manual InfoFrame Register Name Byte Name Map Address 0xE361 vs_inf_pb_0_14 Data Byte 13 0xE362 vs_inf_pb_0_15 Data Byte 14 0xE363 vs_inf_pb_0_16 Data Byte 15 0xE364 vs_inf_pb_0_17 Data Byte 16 0xE365 vs_inf_pb_0_18 Data Byte 17 0xE366 vs_inf_pb_0_19 Data Byte 18...
Page 193 ADV8005 Hardware Reference Manual UG-707 InfoFrame Register Name Packet Byte No. Map Address 0x9E isrc1_pb_0_19 PB18 0x9F isrc1_pb_0_20 PB19 0xA0 isrc1_pb_0_21 PB20 0xA1 isrc1_pb_0_22 PB21 0xA2 isrc1_pb_0_23 PB22 0xA3 isrc1_pb_0_24 PB23 0xA4 isrc1_pb_0_25 PB24 0xA5 isrc1_pb_0_26 PB25 0xA6 isrc1_pb_0_27 PB26...
Page 194: Gamut Metadata Packets
UG-707 ADV8005 Hardware Reference Manual InfoFrame Register Name Packet Byte No. Map Address 0x E3BF isrc2_pb_0_24 PB23 0x E3C0 isrc2_pb_0_25 PB24 0x E3C1 isrc2_pb_0_26 PB25 0x E3C2 isrc2_pb_0_27 PB26 0x E3C3 isrc2_pb_0_28 PB27 As defined by the HDMI 1.4 specifications...
Page 195: Customizing Packet/Infoframe Storage Registers
ADV8005 Hardware Reference Manual UG-707 HDMI Register Name Packet Byte No. Map Address 0xE3DD gamut_mdata_pb_0_26 PB25 0xE3DE gamut_mdata_pb_0_27 PB26 0xE3DF gamut_mdata_pb_0_28 PB27 As defined by the HDMI 1.3 specifications The Gamut Metadata packet registers are considered valid if pkt_det_gamut is set to 1 (refer to Section 8.2.2...
Page 196: Hdmi Section Reset Strategy
UG-707 ADV8005 Hardware Reference Manual vs_packet_id[7:0], HDMI RX Infoframe Map, Address 0xE3EC[7:0] This control is used to set the Vendor Specific InfoFrame ID Function vs_packet_id[7:0] Description 0xxxxxxx Packet type value of packet stored in InfoFrame Map, Address 0x54 to 0x6F...
Page 197: Hdmi Transmitter
ADV8005 Hardware Reference Manual UG-707 6. HDMI TRANSMITTER The HDMI transmitters on the ADV8005 are capable of outputting video data at up to 3 GHz and support 3D video output, ARC (common mode only), and audio output. The dual transmitter variants of...
Page 198 UG-707 ADV8005 Hardware Reference Manual Some registers cannot be written to when the signal on the HPD_TXx input pin is low. When the level on the HPD_TX1 pin goes from high to low, some registers will be reset to their default value.
Page 199: Reset Strategy
ADV8005 Hardware Reference Manual UG-707 6.2. RESET STRATEGY The HDMI Tx, and subsections of it, can be reset in a number of ways. Table 43 Table 44 describe how each of the HDMI Tx maps are reset in response to a number of different events.
Page 200: Source Product Description Infoframe
UG-707 ADV8005 Hardware Reference Manual set_avmute, TX2 Main Map, Address 0xF44B[6] This bit is used to control the SET_AVMUTE signal. Function set_avmute Description 0 (default) Set SET_AVMUTE to 0 Set SET_AVMUTE to 1 clear_avmute, TX2 Main Map, Address 0xF44B[7] This bit is used to control the CLEAR_AVMUTE signal.
Page 201: Spare Packets And Vsi Support
ADV8005 Hardware Reference Manual UG-707 Packet Map Access Type Register Name Default Value Byte Name Address 0xF216 spd_pb19[7:0] 0b00000000 Data Byte 19 0xF217 spd_pb20[7:0] 0b00000000 Data Byte 20 0xF218 spd_pb21[7:0] 0b00000000 Data Byte 21 0xF219 spd_pb22[7:0] 0b00000000 Data Byte 22...
Page 202 UG-707 ADV8005 Hardware Reference Manual Packet Map Address Access Type Register Name Default Value Byte Name 0xF2C5 spare1_pb2[7:0] 0b00000000 Data Byte 2 0xF2C6 spare1_pb3[7:0] 0b00000000 Data Byte 3 0xF2C7 spare1_pb4[7:0] 0b00000000 Data Byte 4 0xF2C8 spare1_pb5[7:0] 0b00000000 Data Byte 5...
Page 203 ADV8005 Hardware Reference Manual UG-707 Packet Map Address Access Type Register Name Default Value Byte Name 0xF2F6 spare2_pb19[7:0] 0b00000000 Data Byte 19 0xF2F7 spare2_pb20[7:0] 0b00000000 Data Byte 20 0xF2F8 spare2_pb21[7:0] 0b00000000 Data Byte 21 0xF2F9 spare2_pb22[7:0] 0b00000000 Data Byte 22...
Page 204: System Monitoring
UG-707 ADV8005 Hardware Reference Manual Packet Map Address Access Type Register Name Default Value Byte Name 0xF3E6 spare4_pb3[7:0] 0b00000000 Data Byte 3 0xF3E7 spare4_pb4[7:0] 0b00000000 Data Byte 4 0xF3E8 spare4_pb5[7:0] 0b00000000 Data Byte 5 0xF3E9 spare4_pb6[7:0] 0b00000000 Data Byte 6...
Page 205: Vsync Interrupt
ADV8005 Hardware Reference Manual UG-707 Table 51: HDMI Tx Interrupt Bits in Main Map Register 0xEC97 Bit Name Bit Position Description bksv_flag_int When set to 1 it indicates that the KSVs from the downstream sink have been read and available in the Memory Map.
Page 206: Video Setup
UG-707 ADV8005 Hardware Reference Manual hdcp_controller_error[3:0], TX2 Main Map, Address 0xF4C8[7:4] (Read Only) This signal is used to readback the error code when the HDCP controller error interrupt HDCP_ERROR_INT is 1. Function hdcp_controller_error[3:0] Description 0000 (default) No error 0001 Bad receiver BKSV...
Page 207: Pixel Repetition
UG-707 The detected VIC is sent in the AVI InfoFrames unless pixel repetition is applied to the video stream transmitted by the ADV8005. When pixel repetition is applied to the video data, the VIC sent in the AVI InfoFrame may be different as the VIC is automatically determined by the ADV8005.
Page 208: Video Related Packets And Infoframes
UG-707 ADV8005 Hardware Reference Manual Max mode: The max mode works in the same way as the automatic mode, except that it always selects the highest pixel repetition factor the Tx core is capable of. This makes the video timing independent of the audio sampling rate. This mode is not typically used.
Page 209: Mpeg Infoframe
ADV8005 Hardware Reference Manual UG-707 Table 54: AVI InfoFrame Configuration Registers HDMI Tx Main Bit Location Access Type Default Value Field or Byte Name Map Address 0xEC52 [2:0] 0b0100 InfoFrame version number 0xEC53 [4:0] 0b01101 InfoFrame length 0xEC54 [7:0] 0b00000000...
Page 210: Gamut Metadata
UG-707 ADV8005 Hardware Reference Manual Table 55: MPEG InfoFrame Configuration Registers Packet Map Access Type Field Name Default Value Byte Name Address 0xF220 mpeg_hb0[7:0] 0b00000000 Header Byte 0 0xF221 mpeg_hb1[7:0] 0b00000000 Header Byte 1 0xF222 mpeg_hb2[7:0] 0b00000000 Header Byte 2...
Page 211 ADV8005 Hardware Reference Manual UG-707 Falling edge of last DE of last field Rising edge of first DE of next field VSync GMP sending window 400 pixel 112 pixel Initiate I2C clocks clocks change after 512 clocks Figure 97: I...
Page 212: Audio Setup
UG-707 ADV8005 Hardware Reference Manual 6.11. AUDIO SETUP 6.11.1. Audio Architecture ADV8005 is capable of receiving audio data in I2S, SPDIF, DSD or High Bit Rate (HBR) formats. When the input audio is captured from the audio input pins, it is then converted into audio packets for transmission over the HDMI output interface.
Page 213: Audio Configuration
ADV8005 Hardware Reference Manual UG-707 6.11.3. Audio Configuration The audio_input_sel[2:0], audio_mode[1:0], i2s_format[1:0] fields must be used to configure the Tx core according to the incoming audio input. Refer to Figure 98 Figure 104 for more information on the audio timing formats. There is a manual control to set the audio sample...
Page 214 UG-707 ADV8005 Hardware Reference Manual mclk_ratio[1:0], TX2 Main Map, Address 0xF40A[1:0] This signal is used to specify the ratio between the audio sampling frequency and the clock described using the N and CTS values. Function mclk_ratio[1:0] Description 128*fs 01 (default)
Page 215: I2S Audio
ADV8005 Hardware Reference Manual UG-707 Input Output audio_input audio_mode I2s_format Audio Clock Pins Encoding ADV8005 Format Packet Type _sel Value Input Input Pin Value Value Signal Mapping 0b011 0b01 0b00 I2S[3:0] SCLK, Normal AUD_IN[4:0] Standard HBR Packet MCLK SCLK MCLK...
Page 216 Refer to Figure 100 Figure 104 for timing diagrams on I2S streams input to the ADV8005. When the ADV8005 is configured to receive a direct AES3 stream, the stream it receives should have IEC60958-like subframes (refer to Figure with the stream formatted as follows: •...
Page 217 ADV8005 Hardware Reference Manual UG-707 i2s_sf[3:0], TX2 Main Map, Address 0xF415[7:4] This signal is used to set the Sampling frequency for I2S audio. This information is used both by the audio Rx and the pixel rep. Other values reserved. Function...
Page 218 UG-707 ADV8005 Hardware Reference Manual subpkt1_r_src[2:0], TX2 Main Map, Address 0xF40F[2:0] This signal is used to specify the source of sub packet 1, right channel. Function subpkt1_r_src[2:0] Description I2S[0], left channel I2S[0], right channel I2S[1], left channel 011 (default) I2S[1], right channel...
Page 219 Use sampling frequency from I2S stream, for SPDIF stream 1 (default) Use sampling frequency from I2C registers Figure 98: IEC60958 Sub Stream Data Validity Flag User Data Channel Status Block Start Flag Figure 99: AES3 Stream Format Input to ADV8005 Rev. A | Page 219 of 317...
Page 220 UG-707 ADV8005 Hardware Reference Manual LRCLK LEFT RIGHT SCLK DATA 32 Clock Slots 32 Clock Slots Figure 100: Timing of Standard I2S Stream Input to ADV8005 LRCLK LEFT RIGHT SCLK DATA MSB-1 MSB-1 MSB extended MSB extended 32 Clock Slots...
Page 221: Spdif Audio
SCLK has a frequency that is 64 times the audio sampling frequency programmed in the audioif_sf[2:0] field. Refer to Table 59 for additional details on the DSD modes supported by the ADV8005. Rev. A | Page 221 of 317...
Page 222: Hbr Audio
Note: When the HBR input stream is coming from an ADI HDMI Rx device or from the Rx section of the ADV8005, the fields listed above are set to the respective default values. Since there is no standard for chip to chip HBR transfer, different settings may be required to map the HBR stream input to the Tx core and a non ADI HDMI Rx device.
Page 223: N And Cts Parameters
ADV8005 Hardware Reference Manual UG-707 6.11.4. N and CTS Parameters The audio data carried across the HDMI link to the downstream sink, which is driven by a TMDS clock only, does not retain the original audio sample clock. The task of recreating this clock at the sink is called Audio Clock Regeneration (ACR). There are varieties of ACR methods that can be implemented in an HDMI sink, each with a different set of performance characteristics.
Page 224: Cts Parameter
UG-707 ADV8005 Hardware Reference Manual 6.11.4.2. CTS Parameter The CTS value is an integer number that satisfies Equation TMDS Average Equation 26: Relationship Between N and CTS 6.11.4.3. Recommended N and Expected CTS Values The recommended values of N for several standard pixel clocks are given in...
Page 225: Audio Sample Packets
ADV8005 Hardware Reference Manual UG-707 32 kHz Pixel Clock (MHz) 148.5/1.001 11648 421875 148.5 4096 148500 Other 4096 Measured Table 62: Recommended N and Expected CTS Values for 44.1 kHz and Multiples 44.1kHz 88.2 kHz 176.4 kHz Pixel Clock (MHz) 25.2 / 1.001...
Page 226 UG-707 ADV8005 Hardware Reference Manual The audio packets use the channel status format conforming to the IEC 60958 specification. When the part is configured to receive an I2S stream, the information sent in the channel status fields is provided by the following fields: •...
Page 227 ADV8005 Hardware Reference Manual UG-707 source_number[3:0], TX2 Main Map, Address 0xF414[7:4] This signal is used to set the Channel Status source number. Function source_number[3:0] Description 0000 (default) Default value xxxx Channel Status source number word_length[3:0], TX2 Main Map, Address 0xF414[3:0] This signal is used to set the Channel Status Audio Word Length.
Page 228 UG-707 ADV8005 Hardware Reference Manual Channel Status Bit Channel Status Bit Name Main Map Bit Location or Fixed Value Main Map Bit Name or Fixed Value Channel number Figure 106 Figure 106 Channel number Figure 106 Figure 106 Channel number...
Page 229 ADV8005 Hardware Reference Manual UG-707 Start Audio Sample Packet Header Layout bit Audio Sample Packet Header Audio Sample Packet Header sample_present.spX bit sample_present.spX bit Audio Sample Subpacket X Audio Sample Subpacket X Cl[23:20] = 2(X) + 1 Cl[23:20] = 1...
Page 230: Audio Infoframe
UG-707 ADV8005 Hardware Reference Manual 6.11.6. Audio InfoFrame The audio InfoFrame allows the sink to identify the characteristics of an audio stream before the channel status information is available. ADV8005 can be configured to transmit audio InfoFrame by setting audioif_pkt_en to 1.
Page 231: Isrc Packet
ADV8005 Hardware Reference Manual UG-707 Table 66: ACP Packet Configuration Registers Packet Map Address Access Type Field Name Default Value Byte Name 0x40 acp_hb0[7:0] 0b00000000 Header Byte 0 0x41 acp_hb1[7:0] 0b00000000 Header Byte 1 0x42 acp_hb2[7:0] 0b00000000 Header Byte 2...
Page 232 UG-707 ADV8005 Hardware Reference Manual Table 67: ISRC1 Packet Configuration Registers Packet Map Address Access Type Field Name Default Value Byte Name 0xF260 isrc1_hb0[7:0] 0b00000000 Header Byte 0 0xF261 isrc1_hb1[7:0] 0b00000000 Header Byte 1 0xF262 isrc1_hb2[7:0] 0b00000000 Header Byte 2...
Page 233: Edid Handling
ADV8005 Hardware Reference Manual UG-707 Packet Map Address Access Type Field Name Default Value Byte Name 0xF290 isrc2_pb13[7:0] 0b00000000 Data Byte 13 0xF291 isrc2_pb14[7:0] 0b00000000 Data Byte 14 0xF292 isrc2_pb15[7:0] 0b00000000 Data Byte 15 0xF293 isrc2_pb16[7:0] 0b00000000 Data Byte 16...
Page 234: Edid_Tries Control
UG-707 ADV8005 Hardware Reference Manual Figure 107 shows how to implement software to read EDID from the downstream sink using the ADV8005. START Wait for HPD interrupt HDP_INT Power up Tx via SYSTEM_PD Wait for EDID Ready Interrupt EDID_SEGMENT EDID_READY_INT...
Page 235: Hdcp Handling
ADV8005 Hardware Reference Manual UG-707 edid_reread, TX2 Main Map, Address 0xF4C9[4] This bit is used to request a the EDID controller to reread the current segment if toggled from 0 to 1 for 10 times consecutively. Function edid_reread Description 0 (default)
Page 236: Multiple Sinks And No Upstream Devices
UG-707 ADV8005 Hardware Reference Manual 6.13.2. Multiple Sinks and No Upstream Devices When connecting the ADV8005 as a source to an HDMI input of a repeater, it is necessary to read all BKSVs from downstream devices. These BKSVs must be checked against a revocation list, which will be provided on the source content.
Page 237 ADV8005 Hardware Reference Manual UG-707 KSV Number Field Name Register Addresses bksv8_byte_0[7:0] 0xEE28[7:0] byte 0 bksv8_byte_1[7:0] 0xEE29[7:0] byte 1 bksv8_byte_2[7:0] 0xEE2A[7:0] byte 2 bksv8_byte_3[7:0] 0xEE2B[7:0] byte 3 bksv8_byte_4[7:0] 0xEE2C[7:0] byte 4 bksv9_byte_0[7:0] 0xEE2D[7:0] byte 0 bksv9_byte_1[7:0] 0xEE2E[7:0] byte 1 bksv9_byte_2[7:0]...
Page 238: Software Implementation
UG-707 ADV8005 Hardware Reference Manual 6.13.3. Software Implementation Figure 108 shows a block diagram of HDCP software implementation for all cases using the ADV8005 Tx HDCP/EDID controller state machine. The necessary interactions with the ADV8005 registers and EDID memory, as well as when these interactions should take place, are illustrated in the diagram.
Page 239: Av Mute
ADV8005 Hardware Reference Manual UG-707 6.13.4. AV Mute AV mute can be enabled once HDCP authentication is completed between the ADV8005 and the downstream sink. This can be used to maintain HDCP synchronization while changing video resolutions. While the KSVs for the downstream devices are being collected, an active HDCP link capable of sending encrypted video is established, but video should not be sent across the link until the KSVs have been compared with the revocation list.
Page 240: Charge Injection Settings
UG-707 ADV8005 Hardware Reference Manual tx1_arc_bias_hyst_adj and tx2_arc_bias_hyst_adj. tx1_arc_bias_hyst_adj, IO Map, Address 0x1A88[1] This bit is used to control the addition of hysteresis to the TX1 ARC. Function tx1_arc_bias_hyst_adj Description 0 (default) Normal ADD hysteresis tx2_arc_bias_hyst_adj, IO Map, Address 0x1A8A[1] This bit is used to control the addition of hysteresis to the TX2 ARC.
Page 241: Hdmi Tx Source Termination
ADV8005 Hardware Reference Manual UG-707 pre_en_clk, TX2 Main Map, Address 0xF480[0] Enable clock channel Function pre_en_clk Description 1 (default) Enabled 0 = Disabled To disable a TMDS output, it is recommended to follow this sequence: Disable the charge injection for the channel...
Page 242: Hdmi Acr Packet Transmission
UG-707 ADV8005 Hardware Reference Manual TX OUTPUT PORT CONNECTED TO SINK DEVICE CAN SINK DEVICE RECEIVE TMDS CLK FREQUENCIES GREATER THAN 165MHz ? IS TX OUTPUT’S TX OUTPUT PORT TX OUTPUT PORT TMDS CLK FREQUENCY SOURCE TERMINATION SOURCE TERMINATION GREATER THAN 165MHz ?
Page 243: Video Encoder Introduction To The Adv8005
ADV8005 Hardware Reference Manual UG-707 7. VIDEO ENCODER INTRODUCTION TO THE ADV8005 7.1. INTRODUCTION ADV8005 encoder core consists of six high speed, Noise Shaped Video (NSV), 12-bit video DACs which provide support for composite (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard definition (SD), enhanced definition (ED), or high definition (HD) video formats.
Page 244 UG-707 ADV8005 Hardware Reference Manual A D V 8 0 05 E N C O D E R P R O C E S S O R M U X 1 4 - B I T D A C 1...
Page 245 ADV8005 Hardware Reference Manual UG-707 hd_enc_ip_mode[4:0], Encoder Map, Address 0xE430[7:3] This signal is used to select the ED/HD output standard. Function hd_enc_ip_mode[4:0] Description 00000 (default) SMPTE293M-1996 483P 60/1.001 OR ITU-R BT.1358 483P 60/1.001 00010 BTA T-1004 EDTV2 483P 60/1.001 OR ITU-R BT.1362 483P 60/1.001 00011 ITU-R BT.1358 576P 50...
Page 246: Output Configuration
UG-707 ADV8005 Hardware Reference Manual Table 70: Standards Directly Supported by ADV8005 Encoder Processor Active Resolution Frame Rate (Hz) Standard 720 × 240 59.94 720 × 288 720 × 480 29.97 ITU-R BT.601/656 720 × 576 ITU-R BT.601/656 720 × 483 59.94...
Page 247: Additional Design Features
ADV8005 Hardware Reference Manual UG-707 dac2_sel[2:0], Encoder Map, Address 0xE429[2:0] This signal selects the data that is supplied to DAC 2. Function dac2_sel[2:0] Description CVBS or Black Burst 1 (default) Luma Chroma Pb/B Pr/R dac3_sel[2:0], Encoder Map, Address 0xE42A[6:4] This signal selects the data that is supplied to DAC 3.
Page 248: Output Oversampling
(this happens with poor video sources like VCRs). Since the color subcarrier in SD modes is generated from the input pixel clock to the ADV8005, these variations on its frequency may alter the final color on the CBVS or Y/C output.
Page 249: Sd Vcr Ff/Rw Synchronization
ADV8005 Hardware Reference Manual UG-707 7.4.3. SD VCR FF/RW Synchronization In DVD record applications where the encoder is used with a decoder, the VCR FF/RW synchronization control bit can be used for nonstandard input video. This is in fast forward or rewind modes.
Page 250: Programming The Fsc
UG-707 ADV8005 Hardware Reference Manual 7.4.5.1. Programming the FSC The subcarrier frequency register value is divided into four FSC registers, as shown in Equation 28. The subcarrier frequency registers (fsc[31:0]) must be updated sequentially, starting with Subcarrier Frequency Register 0 and ending with Subcarrier Frequency Register 3. The reason for this is because the subcarrier frequency only updates when Subcarrier Frequency Register 3 has been updated.
Page 251 ADV8005 Hardware Reference Manual UG-707 Filter Pass-Band Ripple (dB) 3 dB Bandwidth (MHz) Chroma 1.3 MHz 0.09 1.395 Chroma 2.0 MHz 0.048 Chroma 3.0 MHz Monotonic Chroma CIF Monotonic 0.65 Chroma QCIF Monotonic Pass-band ripple is the maximum fluctuation from the 0 dB response in the pass band, measured in decibels. The pass band is defined to have 0 Hz to fc (Hz) frequency limits for a low-pass filter and 0 Hz to f1 (Hz), and f2 (Hz) to infinity for a notch filter, where fc, f1, and f2 are the −3 dB points.
Page 252 UG-707 ADV8005 Hardware Reference Manual –1 FREQUENCY (MHz) Figure 113: SD Luma SSAF Filter, Programmable Gains –1 –2 –3 –4 –5 FREQUENCY (MHz) Figure 114: SD Luma SSAF Filter, Programmable Attenuation peak_en, Encoder Map, Address 0xE487[4] This bit is used to enable the SD SSAF filter gain.
Page 253: Ed/Hd Filters
ADV8005 Hardware Reference Manual UG-707 chroma_filter_sel[2:0], Encoder Map, Address 0xE480[7:5] This signal is used to configure the chroma filters for SD data. Function chroma_filter_sel[2:0] Description 000 (default) 1.3MHz 0.65MHz 1MHz 2MHz Reserved Chroma CIF Chroma QCIF 3MHz In addition to the chroma filters listed with chroma_filter_sel[2:0], there is an SSAF filter that is specifically designed for the color difference component outputs, Pr and Pb.
Page 254: Ed/Hd Test Pattern Generator
UG-707 ADV8005 Hardware Reference Manual –0.1 –0.2 –0.3 –0.4 –0.5 FREQUENCY (MHz) Figure 116: ED/HD Sinc Compensation Filter Enabled –0.1 –0.2 –0.3 –0.4 –0.5 FREQUENCY (MHz) Figure 117: ED/HD Sinc Compensation Filter Disabled sinc_filt_df_en, Encoder Map, Address 0xE433[3] This bit is used to disable the sinc compensation filter on DAC1, DAC2 and DAC3.
Page 255: Color Space Conversion Matrix
ADV8005 Hardware Reference Manual UG-707 The values for the luma (Y) and the color difference (Cr and Cb) signals used to obtain white, black, and saturated primary and complementary colors conform to the ITU-R BT.601-4 standard. Table 74 shows sample color values that can be programmed into the color registers when the output standard selection is set to EIA 770.2/EIA770.3 (Reg 0x30, Bits[1:0] = 00).
Page 256 UG-707 ADV8005 Hardware Reference Manual matrix_prog_en, Encoder Map, Address 0xE402[3] This bit is used to enable the manual mode for the ED/HD colour space converter. Function matrix_prog_en Description 0 (default) Automatic Mode Manual Mode Normally, there is no need to enable this feature because the CSC matrix automatically performs the CSC based on the input mode chosen (ED or HD) and the output color space selected using yuv_out.
Page 257: Programming The Csc Matrix
ADV8005 Hardware Reference Manual UG-707 For example, SMPTE 293M uses the following conversion: R = Y + 1.402Pr G = Y – 0.714Pr – 0.344Pb B = Y + 1.773Pb The programmable CSC matrix is used for external ED/HD pixel data and is not functional when internal test patterns are enabled.
Page 258: Sd Hue Adjust Control
UG-707 ADV8005 Hardware Reference Manual For example, if Scale Factor = 1.3 Y, Cb, or Cr Scale Value = 1.3 × 512 = 665.6 Y, Cb, or Cr Scale Value = 666 (rounded to the nearest integer) Y, Cb, or Cr Scale Value = 1010 0110 10b...
Page 259: Sd Brightness Detect
ADV8005 Hardware Reference Manual UG-707 hue[7:0], Encoder Map, Address 0xE4A0[7:0] This register is used to set the SD hue adjust value. Function hue[7:0] Description 0x00 (default) SD Hue Value 7.4.13. SD Brightness Detect ADV8005 encoder core allows the user to monitor the brightness level of the incoming video data. This feature is used to monitor the average brightness of the incoming Y signal on a field-by-field basis.
Page 260: Double Buffering
UG-707 ADV8005 Hardware Reference Manual Table 76: Sample Brightness Control Values Setup Level (NTSC) with Pedestal Setup Level (NTSC) Without Pedestal Setup Level (PAL) Brightness Control Value setup[6:0] 22.5 IRE 15 IRE 15 IRE 0x1E 15 IRE 7.5 IRE 7.5 IRE 0x0F 7.5 IRE...
Page 261: Programmable Dac Gain Control
ADV8005 Hardware Reference Manual UG-707 7.4.16. Programmable DAC Gain Control It is possible to adjust the DAC output signal gain up or down from its absolute level. This is illustrated in Figure 119. CASE A GAIN PROGRAMMED IN DAC OUTPUT LEVEL...
Page 262: Gamma Correction
UG-707 ADV8005 Hardware Reference Manual dac1to3_tuning[7:0], Encoder Map, Address 0xE40B[7:0] This register is used to set the gain for DACs 1-3 output voltage. Function dac1to3_tuning[7:0] Description 11000000 -7.5% 11000001 -7.382% 11000010 -7.364% 11111111 -0.018% 00000000 (default) 00000001 0.018% 00000010 0.036% 00111111 +7.382%...
Page 263 ADV8005 Hardware Reference Manual UG-707 generate intermediate values. Considering that the curve has a total length of 256 points, the 10 programmable locations are at the following points: 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. The following locations are fixed and cannot be changed: 0, 16, 240, and 255.
Page 264: Ed/Hd Gamma Correction
UG-707 ADV8005 Hardware Reference Manual GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR VARIOUS GAMMA VALUES LOCATION Figure 121: Signal Input (Ramp) and Selectable Output Curves 7.4.17.1. ED/HD Gamma Correction To enable the gamma correction curves for ED/HD standards, gamma_en_hdtv must be programmed.
Page 265: Sd Gamma Correction
ADV8005 Hardware Reference Manual UG-707 To select between both the A and B curves for the ED/HD gamma correction, the gamma_curve_b_hdtv must be programmed. gamma_curve_b_hdtv, Encoder Map, Address 0xE435[4] This bit is used to select the gamma correction curves for ED/HD video data.
Page 266: Ed/Hd Sharpness Filter And Adaptive Filter Controls
UG-707 ADV8005 Hardware Reference Manual 7.4.18. ED/HD Sharpness Filter and Adaptive Filter Controls There are three filter modes available on the ADV8005 encoder block: a sharpness filter mode and two adaptive filter modes. 7.4.18.1. ED/HD Sharpness Filter Mode To enhance or attenuate the Y signal in the frequency ranges shown in...
Page 267: Ed/Hd Adaptive Filters
ADV8005 Hardware Reference Manual UG-707 ka[3:0], Encoder Map, Address 0xE440[3:0] This signal is used to configure the ED/HD sharpness filter gain, value A. Function ka[3:0] Description 0000 (default) Gain A 0 0001 Gain A +1 0111 Gain A +7 1000...
Page 268: Ed/Hd Adaptive Filter Modes
UG-707 ADV8005 Hardware Reference Manual fil_resp_aa[3:0], Encoder Map, Address 0xE458[3:0] This signal is used to set the adaptive filter gain 1 for the ED/HD standard. This is value A. Function fil_resp_aa[3:0] Description 0000 (default) Gain A 0 0001 Gain A +1...
Page 269: Ed/Hd Sharpness Filter And Adaptive Filter Application Examples
ADV8005 Hardware Reference Manual UG-707 Mode B is used when ED/HD adaptive filter mode control is set to 1. In this mode, a cascade of filter A and filter B is used. Both settings for Gain A and Gain B in the ED/HD sharpness filter gain register and ED/HD adaptive filter (Gain 1, Gain 2, and Gain 3) registers become active when needed.
Page 270 UG-707 ADV8005 Hardware Reference Manual Register Register Setting 0xE401 0x38 0xE402 0x20 0xE430 0x00 0xE431 0x81 0xE435 0x80 0xE440 0x00 0xE458 0xAC 0xE459 0x9A 0xE45A 0x88 0xE45B 0x28 0xE45C 0x3F 0xE45D 0x64 Figure 124: Input Signal to ED/HD Adaptive Filter...
Page 271: Sd Digital Noise Reduction
ADV8005 Hardware Reference Manual UG-707 Figure 126: Output Signal from ED/HD Adaptive Filter (Mode B) 7.4.19. SD Digital Noise Reduction ADV8005 encoder block offers a feature for digital noise reduction (DNR). DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal (DNR input select).
Page 272: Coring Gain Border
UG-707 ADV8005 Hardware Reference Manual MPEG1 systems (block size control). DNR can be applied to the resulting block transition areas that are known to contain noise. Generally, the block transition area contains two pixels. It is possible to define this area to contain four pixels (border area).
Page 273: Dnr Threshold
ADV8005 Hardware Reference Manual UG-707 dnr_coring_gain_b[3:0], Encoder Map, Address 0xE4A3[3:0] This signal is used to configure the coring gain data (in Digital Noise Reduction (DNR) mode, the values in brackets apply). Function dnr_coring_gain_b[3:0] Description 0000 (default) No gain 0001 +1/16 [−1/8] 0010 +2/16 [−2/8]...
Page 274: Dnr Input Select Control
UG-707 ADV8005 Hardware Reference Manual dnr_mpeg_1, Encoder Map, Address 0xE4A4[7] This bit is used to select the Digital Noise Reduction (DNR) block size. Function dnr_mpeg_1 Description 16 pixels 0 (default) 8 pixels 7.4.19.6. DNR Input Select Control dnr_fmode_control[2:0] is used to select the filter which is applied to the incoming Y data. The signal that lies in the pass band of the selected filter is the signal that is DNR processed.
Page 275: Dnr Block Offset Control
ADV8005 Hardware Reference Manual UG-707 7.4.19.8. DNR Block Offset Control blk_offset[3:0] allows a shift of the data block of 15 pixels maximum. The coring gain positions are fixed. The block offset shifts the data in steps of one pixel so that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data.
Page 276: Vertical Blanking Interval
UG-707 ADV8005 Hardware Reference Manual VOLTS IRE:FLT L135 –50 –2 Figure 133: Example of Video Output with SD Active Video Edge Control Enabled slope_en, Encoder Map, Address 0xE482[7] This bit is used to enable the SD active video edge control.
Page 277: Dac Configurations
ADV8005 Hardware Reference Manual UG-707 vbi_open, Encoder Map, Address 0xE483[4] This bit is used to enable data on the Vertical Blanking Interval (VBI) to be accepted as valid data. This is valid for SD video data only. Function vbi_open Description Enabled 0 ...
Page 278 UG-707 ADV8005 Hardware Reference Manual 10µH OUTPUT 75Ω 600Ω 22pF 600Ω OUTPUT 560Ω 560Ω Figure 134: Example of Output Filter for SD, 16× Oversampling 4.7µH OUTPUT 75Ω 600Ω 6.8pF OUTPUT 600Ω 6.8pF 560Ω 560Ω Figure 135: Example of Output Filter for ED, 8× Oversampling...
Page 279 ADV8005 Hardware Reference Manual UG-707 CIRCUIT FREQUENCY RESPONSE –10 MAGNITUDE (dB) –20 –30 PHASE GROUP DELAY (Seconds) (Degrees) –40 –50 –60 –80 –70 –160 –80 –240 –90 100M FREQUENCY (Hz) Figure 138: Output Filter Plot for ED, 8× Oversampling CIRCUIT FREQUENCY RESPONSE...
Page 280: Interrupts
UG-707 ADV8005 Hardware Reference Manual 8. INTERRUPTS ADV8005 has a comprehensive set of interrupt registers located in the IO Map and HDMI Main Maps of both the Serial Video Rx and HDMI transmitters. These interrupts can be used to indicate certain events in the Serial Video Rx section, OSD, and VSP, and also the HDMI Tx.
Page 281: Storing Masked Interrupts
Store triggered interrupts 8.2. SERIAL VIDEO RX INTERRUPTS 8.2.1. Introduction This section describes the interrupt support provided for the Serial Video Rx on the ADV8005. The Serial Video Rx interrupts are OR’ d together and connected to the ADV8005 INT2 pin.
Page 282 UG-707 ADV8005 Hardware Reference Manual xxx_RAW xxx_ST Interrupt path for level sensitive Interrupts CHANGE Internal DETECTION HOLD UNTIL APPLY SAMPLING Status Flag (Rising and CLEARED MASK Falling edge) xxx_CLR xxx_MB1 Output yyy_CLR yyy_MB1 Interrupt path for edge CHANGE sensitive Interrupts...
Page 283 ADV8005 Hardware Reference Manual UG-707 New AVI InfoFrame Detection Internal Pulse Flag AVI InfoFrame with new content detected Time > 2 xtal periods NEW_AVI_INFO_RAW NEW_AVI_INFO_ST NEW_AVI_INFO_CLR set to 1 Time taken by the CPU to clear NEW_AVI_INFO_ST Figure 142: NEW_AVI_INFO_RAW and NEW_AVI_INFO_ST Timing All raw bits have corresponding status bits.
Page 284: Interrupt Architecture Overview
UG-707 ADV8005 Hardware Reference Manual edge_sensitive_int _clr, IO, Address 0xXX (Self-Clearing) This control is used to clear the edge_sensitive_int_raw and edge_sensitive_int_st bits. This is a self clearing bit. Function edge_sensitive_int_clr Description 0  No function Clear edge_sensitive_int_raw and edge_sensitive_int_st level_sensitive_int_mb2, IO, Address 0xXX[0] This control is used to set the INT2 interrupt mask for the level_sensitive_int interrupt.
Page 285: Multiple Interrupt Events
ADV8005 Hardware Reference Manual UG-707 Table 85: Serial Video Rx Edge Sensitive Interrupts Interrupt Mode of Operation Description rx_vs_inf_cks_err_ Edge sensitive Used to indicate if there was an error with the vendor specific InfoFrame edge_raw/st/mb2/clr rx_ms_inf_cks_err Edge sensitive Used to indicate if there was an error with the MPEG source InfoFrame...
Page 286: Interrupt Architecture Overview
VSP interrupt is inverted logical OR of VSP/OSD interrupts 8.4. HDMI TX CORE 8.4.1. Introduction This section describes the interrupt support provided for the HDMI Tx cores of the ADV8005. The HDMI Tx interrupts are OR’ d together and connected to the ADV8005 INT1 pin.
Page 287: Interrupt Architecture Overview
ADV8005 Hardware Reference Manual UG-707 8.4.2. Interrupt Architecture Overview The following is a complete list of HDMI Tx interrupts and their descriptions: Table 87: HDMI Tx Interrupts Interrupt Description hpd_int/ hpd_int_en Used to indicate the HDMI transmitter is connected to an HDMI Rx...
Page 288: Pcb Layout Recommendations
A solid plane must be maintained underneath the encoder analog outputs for their full trace length. The termination resistors on the encoder analog outputs should be kept as close as possible to the ADV8005. Any external filtering on the encoder outputs should be placed as close as possible to the analog connectors.
Page 289: Power Supply Bypassing
It is recommended to use a single ground plane for the ADV8005. Careful attention must be paid to the layout of any internal power supply planes when traces run on adjacent layers – traces on a layer directly above or below a power supply layer must not cross between two power supply planes as this will impact the return current paths.
Page 290: Encoder Component Placement
3.3 V and one 1.8 V. The recommended power supply design is illustrated in Figure 145. If using more than one 1.8 V regulator to supply ADV8005, it must be ensured that DVDD_DDR, PVDD_DDR and DVDD are supplied by the same regulator. The power-up sequence of the...
Page 291 ADV8005 Hardware Reference Manual UG-707 3 . 3 V R e g u l a t o r F i l t e r A V D D 1 F i l t e r A V D D 2...
Page 292: Unused Pin List
UG-707 ADV8005 Hardware Reference Manual APPENDIX B UNUSED PIN LIST Pin Type Location Mnemonic Type Description if Unused OSD_IN[23]/EXT_DIN[7] OSD video Float this pin as it is disabled by default. Bi-directional digital IO input/ miscellaneous digital OSD_DE OSD video Float this pin as it is disabled by default.
Page 293 ADV8005 Hardware Reference Manual UG-707 Pin Type Location Mnemonic Type Description if Unused ARC1_OUT Audio output Connect this pin to ground through a Digital output 4.7kΩ resistor. MISO1 Serial port Float this pin as it is disabled by default. Digital output...
Page 294 UG-707 ADV8005 Hardware Reference Manual Pin Type Location Mnemonic Type Description if Unused AVDD1 Power Serial Video Rx Inputs Analog Supply (3.3 AVDD1 Power Serial Video Rx Inputs Analog Supply (3.3 DAC5 Analog video Float this pin. Analog output output...
Page 295 ADV8005 Hardware Reference Manual UG-707 Pin Type Location Mnemonic Type Description if Unused OSD_IN[14]/VBI_MOSI OSD video Float this pin as it is disabled by default. Bi-directional digital IO input/ miscellaneous digital OSD_IN[15]/VBI_CS OSD video Float this pin as it is disabled by default.
Page 296 UG-707 ADV8005 Hardware Reference Manual Pin Type Location Mnemonic Type Description if Unused Ground. AVDD3 Power HDMI Analog Power Supply (1.8 V). OSD_IN[1] OSD video Float this pin as it is disabled by default. Bi-directional digital IO input OSD_IN[2] OSD video Float this pin as it is disabled by default.
Page 297 ADV8005 Hardware Reference Manual UG-707 Pin Type Location Mnemonic Type Description if Unused PCLK Digital Video Float this pin as it is disabled by default. Digital input Sync DVDD_IO Power Digital Interface Supply (3.3 V). DVDD_IO Power Digital Interface Supply (3.3 V).
Page 298 UG-707 ADV8005 Hardware Reference Manual Pin Type Location Mnemonic Type Description if Unused Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. R_TX1 HDMI Tx11 Float this pin. Digital output PVDD5 Power HDMI Tx PLL Power Supply (1.8 V). This pin is a voltage regulator output.
Page 299 ADV8005 Hardware Reference Manual UG-707 Pin Type Location Mnemonic Type Description if Unused P[23] Digital video Float this pin as it is disabled by default. Digital input input DVDD Power Digital Power Supply (1.8 V). Ground. Ground. Ground. Ground. Ground.
Page 300 UG-707 ADV8005 Hardware Reference Manual Pin Type Location Mnemonic Type Description if Unused Ground. Ground. Ground. Ground. Ground. Ground. HPD_TX2 HDMI Tx2 Float this pin. Analog input Ground. TX2_0+ HDMI Tx2 Float this pin. Digital output TX2_0− HDMI Tx2 Float this pin.
Page 301 ADV8005 Hardware Reference Manual UG-707 Pin Type Location Mnemonic Type Description if Unused P[3] Digital video Float this pin as it is disabled by default. Digital input input P[4] Digital video Float this pin as it is disabled by default.
Page 302 Connect this pin to ground through a Bi-directional digital IO 4.7kΩ resistor. NC/GND For New ADV8005 Designs, Float this connect/GND pin. For Designs That Must Maintain Consistency with ADV8005, this Pin can be Grounded. DDR_A[8] DDR interface Float this pin. Digital output AA10 DVDD_DDR Power DDR Interface Supply (1.8 V).
Page 303 ADV8005 Hardware Reference Manual UG-707 Pin Type Location Mnemonic Type Description if Unused AB20 DDR_DQ[0] DDR interface Connect this pin to ground through a Bi-directional digital IO 4.7kΩ resistor. AB21 DDR_DQ[5] DDR interface Connect this pin to ground through a Bi-directional digital IO 4.7kΩ...
Page 304: Pixel Input And Output Formats
UG-707 ADV8005 Hardware Reference Manual APPENDIX C PIXEL INPUT AND OUTPUT FORMATS Rev. A | Page 304 of 317...
Page 305 ADV8005 Hardware Reference Manual UG-707 Table 88: RGB Input Formats ADV8005 8-BIT DDR 10-BIT DDR 12-BIT DDR 4:2:2 4:2:2 4:2:2 NAME 4:4: 4:2: 4:2: 4:2: 4:2: 4:2: 4:2: 4:4: 4:4: 4:4: 4:4: 4:4: 4:4: 4:4: 4:2: 4:2: 4:2: Cloc Cloc...
Page 306 UG-707 ADV8005 Hardware Reference Manual OSD_IN. OSD_IN. OSD_IN. OSD_IN. OSD_IN. P.35 P.34 P.33 P.32 P.31 P.30 P.29 P.28 P.27 P.26 Inpu P.25 P.24 P.23 P.22 P.21 P.20 P.19 P.18 P.17 P.16 Rev. A | Page 306 of 317...
Page 307 ADV8005 Hardware Reference Manual UG-707 P.15 P.14 P.13 P.12 P.11 P.10 Rev. A | Page 307 of 317...
Page 308 UG-707 ADV8005 Hardware Reference Manual Table 89: YCbCr Input Formats 8005 8-BIT 12-BIT 8-BIT DDR 10-BIT DDR 12-BIT DDR 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2: 4:2: 4:4: 4:4: 4:4: 4:2:2 4:2:2 4:4: 4:4: 4:4: 4:4: 4 (a) 4:4: 4:2: 4:2:...
Page 309 ADV8005 Hardware Reference Manual UG-707 _IN.1 Cb1/Cr Cb1, 1,Y1 _IN.1 Cb0/Cr Cb0, 0,Y0 Y1.1 Y1.7 Y1.7 Y1.9 _IN.1 Cb7, Cb9, 1,Cr Y1.1 Y1.6 Y1.6 Y1.8 _IN.1 Cb6, Cb8, 0,Cr Cb5, Cb7, Cb9, Y1.5 Y1.5 Y1.7 Y1.9 _IN.9 Cb4, Cb6, Cb8, Y1.4...
Page 310 UG-707 ADV8005 Hardware Reference Manual Cr1. Cb.1 Cb.3 P.27 Cr1. Cb.0 Cb.2 P.26 Cr1. Cb.1 P.25 Cr1. Cb.0 P.24 Cb7/ Cb9/ Cb11/ Cr7, Cr9, Cr11,Y Cb7, Cb9, 1,Cr P.23 Cb6/ Cb8/ Cb10/ Cr6, Cr8, Cr10,Y Cb6, Cb8, 0,Cr P.22 Cb5/...
Page 311 ADV8005 Hardware Reference Manual UG-707 Cb4, Cb6, Cb8, Cr.4 Cr.6 Cr.8 Cb3, Cb5, Cb7, Cr2. Cr.3 Cr.5 Cr.7 Cb2, Cb4, Cb6, Cr2. Cr.2 Cr.4 Cr.6 Cb1, Cb3, Cb5, Cr2. Cr.1 Cr.3 Cr.5 Cb0, Cb2, Cb4, Cr2. Cr.0 Cr.2 Cr.4 Cb1, Cb3, Cr2.
Page 312 UG-707 ADV8005 Hardware Reference Manual Table 90: Alpha Blending Input Formats Alpha Format OSD_DE OSD_VS OSD_CLK OSD_IN.23 OSD_IN.22 OSD_IN.21 OSD_IN.20 OSD_IN.19 OSD_IN.18 OSD_IN.17 OSD_IN.16 OSD_IN.15 OSD_IN.14 OSD_IN.13 OSD_IN.12 OSD_IN.11 OSD_IN.10 OSD_IN.9 OSD_IN.8 OSD_IN.7 OSD_IN.6 OSD_IN.5 OSD_IN.4 OSD_IN.3 OSD_IN.2 OSD_IN.1 OSD_IN.0 P.35...
Page 313 ADV8005 Hardware Reference Manual UG-707 P.29 P.28 P.27 P.26 P.25 P.24 P.23 P.22 P.21 P.20 P.19 P.18 P.17 P.16 P.15 P.14 P.13 P.12 P.11 P.10 VID_DE VID_HS VID_VS VID_CLK Rev. A | Page 313 of 317...
Page 314 UG-707 ADV8005 Hardware Reference Manual Table 91: RGB TTL Output Formats ADV8005 24-BIT SDR 4:4:4 30-BIT SDR 4:4:4 36-BIT SDR 4:4:4 NAME OSD_DE DE_OUT DE_OUT DE_OUT OSD_VS VS_OUT VS_OUT VS_OUT OSD_HS HS_OUT HS_OUT HS_OUT OSD_CLK CLK_OUT CLK_OUT CLK_OUT OSD_IN.23 OSD_IN.23 OSD_IN.21...
Page 315 ADV8005 Hardware Reference Manual UG-707 P.17 P.16 P.15 P.14 P.13 P.12 P.11 P.10 Table 92: YCrCb TTL Output Formats ADV8005 16-BIT SDR 4:2:2 20-BIT SDR 4:2:2 24-BIT SDR 4:2:2 24-BIT SDR 4:4:4 30-BIT SDR 4:4:4 36-BIT SDR 4:4:4 NAME YCbCr Colorspace...
Page 316 UG-707 ADV8005 Hardware Reference Manual OSD_IN.1 Cb1,Cr1 OSD_IN.0 Cb0,Cr0 P.35 Cb11 P.34 Cb10 P.33 P.32 P.31 P.30 P.29 P.28 P.27 P.26 P.25 P.24 P.23 P.22 P.21 P.20 P.19 P.18 P.17 P.16 P.15 P.14 P.13 P.12 P.11 P.10 VID_DE VID_HS VID_VS VID_CLK Rev.
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Analog Devices ADV8005 Hardware Reference Manual

Understanding the ADV8005 Hardware Manual

1 Introduction to the ADV8005

2 ADV8005 Top Level Control

3 Video Signal Processing

4 On Screen Display

5 Serial Video Receiver

6 HDMI Transmitter

7 Video Encoder Introduction to the ADV8005

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