Storing Masked Interrupts; Serial Video Rx Interrupts; Introduction - Analog Devices ADV8005 Hardware Reference Manual

ADV8005 Hardware Reference Manual
8.1.2.

Storing Masked Interrupts

store_unmasked_irqs, IO Map, Address 0x1A69[7]
This bit is used to specify whether the HDMI status flags for any HDMI interrupt should be triggered regardless of whether the mask bits are
set. This bit allows an HDMI interrupt to trigger and allows this interrupt to be read back through the corresponding status bit without
triggering an interrupt on the interrupt pin. The status is stored until the clear bit is used to clear the status register and allows another
interrupt to occur.
Function
store_unmasked_irqs
0 (default)
1

8.2. SERIAL VIDEO RX INTERRUPTS

8.2.1.

Introduction

This section describes the interrupt support provided for the Serial Video Rx on the ADV8005. The Serial Video Rx interrupts are OR' d together
and connected to the ADV8005
The ADV8005 Serial Video Rx interrupt architecture provides the following types of bits:
•
Raw bits
•
Status bits
•
Interrupt mask bits
•
Clear bits
Raw bits are defined as being either edge-sensitive or level-sensitive. The following compares an edge-sensitive interrupt and a level-sensitive
interrupt to demonstrate the difference.
level_sensitive_int_raw, IO, Address 0xXX (Read Only)
This readback indicates the raw status of the level sensitive interrupt. This bit is set to one when a condition occurs and is reset to 0 when the
condition is no longer apparent.
Function
level_sensitive_int_raw
0 
1
edge_sensitive_int_raw, IO, Address 0xXX (Read Only)
This readback indicates the status of the edge sensitive interrupt. When set to 1, it indicates that an event has occurred. Once set, this bit
remains high until the interrupt is cleared via edge_sensitive_int_clr.
Function
edge_sensitive_int_raw
0 
1
Level-sensitive bit, level_sensitive_int_raw, always represents the current status of whether or not a particular event or condition is occurring,
e.g. if the part is receiving AVI InfoFrames. It is not a latched bit and never requires to be cleared.
Edge-sensitive bit, edge_sensitive_int_raw, indicates that a transient event or condition has occurred; it is latched and it needs to be cleared.
This approach is adopted for important events which have a transient nature e.g. if the part has received a new AVI InfoFrame. If
edge_sensitive_int_raw did not latch and returned to 0 sometime after the event occurred, the user could miss the fact that the event or condition
occurred. Therefore, edge-sensitive raw bits do not truly represent the current status; instead, they represent the status of an edge event that
happened in the past. To clear a latched bit, the user must set the corresponding clear bit to 1.
Figure 140, Figure 141 and Figure 142
Description
Do not store triggered interrupts
Store triggered interrupts
INT2 pin.
Description
Event/condition not currently occurring
Event/condition currently occurring
Description
No event/condition occurred
Event/condition occurred
provide a graphical example of what how edge and level sensitive interrupts operate.
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