List Of Figures - Analog Devices ADV8003 Hardware Manual

ADV8003 Hardware Manual

LIST OF FIGURES

Figure 1: Field Description Format ................................................................................................................................................................................ 13
Figure 2: ADV8003 Digital Video Interface .................................................................................................................................................................. 17
Figure 3: ADV8003 Video Processing ............................................................................................................................................................................ 17
Figure 4: ADV8003 Bitmap OSD .................................................................................................................................................................................... 18
Figure 5: External DDR2 Memory Interface ................................................................................................................................................................. 19
Figure 6: ADV8003 Block Diagram ............................................................................................................................................................................... 21
Figure 7. ADV8003KBCZ-8 and ADV8003KBCZ-7 Pin Configuration .................................................................................................................. 22
Figure 8. ADV8003KBCZ-8B and ADV8003KBCZ-7B Pin Configuration ............................................................................................................. 34
Figure 9. ADV8003KBCZ-8C and ADV8003KBCZ-7C Pin Configuration ............................................................................................................ 45
Figure 10. ADV8003KBCZ-7T Pin Configuration ...................................................................................................................................................... 56
Figure 11: Register Map Architecture ............................................................................................................................................................................ 67
Figure 12: Bus Data Transfer ........................................................................................................................................................................................... 68
Figure 13: Read and Write Sequence ............................................................................................................................................................................. 68
Figure 14: ADV8003 Simplified Block Diagram .......................................................................................................................................................... 69
Figure 15: ADV8003 Mode 1 Configuration ................................................................................................................................................................ 72
Figure 16: ADV8003 Mode 2 Configuration ................................................................................................................................................................ 73
Figure 17: ADV8003 Mode 3 Configuration ................................................................................................................................................................ 74
Figure 18: ADV8003 Mode 4 Configuration ................................................................................................................................................................ 75
Figure 19: ADV8003 Mode 5 Configuration ................................................................................................................................................................ 76
Figure 20: ADV8003 Mode 6 Configuration ................................................................................................................................................................ 77
Figure 21: ADV8003 Mode 7 Configuration ................................................................................................................................................................ 78
Figure 22: ADV8003 Mode 8 Configuration ................................................................................................................................................................ 79
Figure 23: ADV8003 Mode 9 Configuration ................................................................................................................................................................ 80
Figure 24: ADV8003 Mode 10 Configuration .............................................................................................................................................................. 81
Figure 25: ADV8003 Mode 11 Configuration .............................................................................................................................................................. 82
Figure 26: ADV8003 Mode 12 Configuration .............................................................................................................................................................. 83
Figure 27: ADV8003 Mode 13 Configuration .............................................................................................................................................................. 84
Figure 28: ADV8003 Mode 14 Configuration .............................................................................................................................................................. 85
Figure 29: ADV8003 Digital Core Muxing ................................................................................................................................................................... 86
Figure 30: Video TTL Input Channel ............................................................................................................................................................................. 89
Figure 31: EXOSD TTL Input Channel ......................................................................................................................................................................... 90
Figure 32: RX Input Channel .......................................................................................................................................................................................... 90
Figure 33: TTL Output Block Diagram ......................................................................................................................................................................... 91
Figure 34: DDR Mode, Luma and Chroma Swap......................................................................................................................................................... 94
Figure 35: Contrast Processing ....................................................................................................................................................................................... 98
Figure 36: Brightness Processing .................................................................................................................................................................................... 99
Figure 37: Saturation Processing .................................................................................................................................................................................. 100
Figure 38: DDR Mode, Luma and Chroma Swap....................................................................................................................................................... 101
Figure 39: Updither Operation ..................................................................................................................................................................................... 106
Figure 40: Configuring Input Port Clock .................................................................................................................................................................... 107
Figure 41: PVSP/SVSP Output Clock Configure........................................................................................................................................................ 110
Figure 42: DDR2 PLL Architecture .............................................................................................................................................................................. 115
Figure 43: DDR2 Loopback Test Architecture ............................................................................................................................................................ 117
Figure 44: VBI Data Extraction Block Diagram ......................................................................................................................................................... 120
Figure 45: ADV8003 Image Processing Colorimetry Breakdown ........................................................................................................................... 125
Figure 46: 720(1440) x 240p @ 59.94/60Hz, CEA Formats 8 and 9 ......................................................................................................................... 130
Figure 47: Primary Input Channel CSC ...................................................................................................................................................................... 131
Figure 48: Secondary Input Channel CSC .................................................................................................................................................................. 134
Figure 49: RX Input Channel CSC ............................................................................................................................................................................... 137
Figure 50: HDMI TX CSC ............................................................................................................................................................................................. 140
Figure 51: ADV8003 PVSP ............................................................................................................................................................................................ 144
Rev. B, August 2013 431