svsp_rb_min_latency[14:0], Secondary VSP Map, Address 0xE6F7[7:0]; Address 0xE6F8[7:1] (Read Only)
This signal is used to read back the minimum frame/HSync latency. The upper three bits are VSync latency, the lower twelve bits are
HSync latency.
Function
svsp_rb_min_latency[1
4:0]
0xXXX
3.3.1.6. Freezing Output Video
Output video can be frozen by disabling the VIM by setting
3.3.2.
SVSP Video Input Module (VIM)
Figure 61
shows the structure of the SVSP VIM. This can be broken up into three hardware blocks. The VIM cropper can be used to crop
an input video image to a given image size. The scaler can be used to scale a video resolution to any target resolution. The pixel packer is
used to pack pixels data into memory words and write them into external memory. The starting address in external memory is provided
by FFS and is configured by the user using the frame buffer registers. As indicated at the start of
to operate, it must first be enabled. This can be done using the
output video will be frozen.
3.3.2.1. VIM Cropper
The VIM cropper block is used to define a sub window within the given input resolution. This cropped image will then become the video
which will be processed by the SVSP. The following registers are used to define this sub window.
•
svsp_vim_crop_enable
•
svsp_vim_crop_h_start[10:0]
•
svsp_vim_crop_v_start[10:0]
•
svsp_vim_crop_width[10:0]
•
svsp_vim_crop_height[10:0]
To enable cropper block in VIM,
svsp_vim_crop_enable, Secondary VSP Map, Address 0xE662[6]
Rev. B, August 2013
Description
Minimum of frame latency
Video Input Module (VIM)
Video Input Module (VIM)
Input
Input
VIM
VIM
Video
Video
Cropper
Cropper
Figure 61: SVSP Video Input Module
svsp_vim_crop_enable
must be set to 1.
svsp_enable_vim
to 0.
Horizontal/Vertical
Horizontal/Vertical
Scaler
Scaler
Pixel
Pixel
Packer
Packer
Write to
Write to
DDR2
DDR2
svsp_enable_vim
bit. If the VIM is disabled by setting this register to 0, the
189
ADV8003 Hardware Manual
FFS
FFS
Section 3.3,
in order for the VIM module
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