Multiple Interrupt Events; Serial Video Interrupts Validity Checking Process; Vsp And Osd Section; Interrupt Architecture Overview - Analog Devices ADV8003 Hardware Manual

Interrupt
rx_gamut_mdata_
pckt_edge_raw/st/mb2/clr
rx_isrc2_pckt_edg
eraw/st/mb2/clr
rx_isrc1_pckt_edg
eraw/st/mb2/clr
rx_vs_info_frm_e
dge_raw/st/mb2/clr
rx_ms_info_frm_e
dge_raw/st/mb2/clr
rx_spd_info_frm_
edge_raw/st/mb2/clr
rx_avi_info_frm_e
dge_raw/st/mb2/clr

9.2.2.1. Multiple Interrupt Events

If an interrupt event occurs, and then a second interrupt event occurs before the system controller has cleared or masked the first
interrupt event, the ADV8003 does not generate a second interrupt signal. The system controller should check all unmasked interrupt
status bits as more than one may be active.
9.2.3.

Serial Video Interrupts Validity Checking Process

All Serial Video interrupts have a set of conditions that must be taken into account for validation in the system firmware. When the
ADV8003 alerts the system controller with a Serial Video interrupt, the host must check that the following validity conditions for that
interrupt are met before processing that interrupt. This is valid for all the interrupts described above.
• ADV8003 is configured in HMDI mode
• rx_tmds_clk_det_raw
• rx_tmdspll_lck_raw

9.3. VSP AND OSD SECTION

This section describes the interrupts provided by the ADV8003 OSD and VSP section. These interrupts are not accessed through the I2C
interface as the interrupts for the Serial Video Rx and HDMI Tx are; these interrupts are accessed through the SPI interface. These
interrupts are not documented in detail as they are handled transparently to the user by the Blimp OSD software tool. Interrupts from this
section are output on the INT0 pin for use by the system microcontroller.
9.3.1.

Interrupt Architecture Overview

The following three interrupts are required by the VSP and OSD section:
Interrupt
OSD_CFG_DONE
DMA_IRQ
DMA_RAM_IRQ
TIMER_IRQ
Rev. B, August 2013
Mode of Operation
Edge sensitive
Edge sensitive
Edge sensitive
Edge sensitive
Edge sensitive
Edge sensitive
Edge sensitive
is set to 1 if the Serial Video Rx input is being used
bit is set to 1

Table 92: VSP and OSD Interrupts

Description
Used to indicate to the system controller that the configuration within
the ADV8003 RAM memories has completed
Used to indicate to the system controller that the current DMA
operation has taken place
Used to indicate to the system controller that the DMA hardware block
can be read from/written to by SPI
Used to indicate to the system controller that a timer has expired
Description
Used to indicate if a gamut metadata packet was detected
Used to indicate if an ISRC2 packet was detected
Used to indicate if an ISRC1 packet was detected
Used to indicate if a vendor specific InfoFrame was detected
Used to indicate if an MPEG source InfoFrame was detected
Used to indicate if a source product descriptor InfoFrame was detected
Used to indicate if an AVI InfoFrame was detected
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ADV8003 Hardware Manual