System Monitoring; General Status And Interrupts; Edid/Hdcp Controller Status; Table 52: Hdmi Tx Interrupt Bits In Hdmi Tx Main Map Register 0Xec96 - Analog Devices ADV8003 Hardware Manual

Packet Map
Address
0xF2F7
0xF2F8
0xF2F9
0xF2FA
0xF2FB
0xF2FC
0xF2FD
0xF2FE

6.7. SYSTEM MONITORING

6.7.1.

General Status and Interrupts

The ADV8003 utilizes both interrupts and status bits to indicate the status of internal operations and errors in the Tx core. These interrupt
and status are listed in Table
Bit Name
hdcp_authenticated_int
edid_ready_int
vsync_int
rx_sense_int
hpd_int
Bit Name Bit Position
bksv_flag_int 6
hdcp_error_int 7
Bit Name
hpd_state
rx_sense_state

6.8. EDID/HDCP CONTROLLER STATUS

The Tx core features an EDID/HDCP controller which handles EDID extraction from the downstream sink. This EDID/HDCP controller
also handles HDCP authentication with downstream sink. The tasks that the Tx EDID/HDCP controller performs are described in
Section 6.12 and Section 6.13.
The current state of the Tx EDID/HDCP controller can be read from the
hdcp_controller_state[3:0], TX2 Main Map, Address 0xF4C8[3:0] (Read Only)
Rev. B, August 2013
Access Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
52, Table 53, and Table 54. Refer to Section 9.4 for details on the use of Tx interrupts.

Table 52: HDMI Tx Interrupt Bits in HDMI Tx Main Map Register 0xEC96

Bit Position Description
1 (Second LSB) When set to 1 it indicates that HDCP/EDID state machine transitioned from state 3 to state 4.
Once set, it remains high until it is cleared by setting it to 1.
2 When set to 1 it indicates that EDID has been read from Rx and is available in Packet Map.
Once set, it remains high until it is cleared by setting it to 1.
5 When set to 1 it indicates that leading edge detected on VSync input to Tx core. Once set, it
remains high until it is cleared by setting it to 1.
6 When set to 1 it indicates that TMDS clock lines voltage has crossed 1.8 V from high to low or
low to high. Once set, it remains high until it is cleared by setting it to 1.
7 When set to 1 it indicates that transition for high to low or low to high was detected on
input HPD signal. Once set, it remains high until it is cleared by setting it to 1.

Table 53: HDMI Tx Interrupt Bits in Main Map Register 0xEC97

Description
When set to 1 it indicates that the KSVs from the downstream sink have been read and available in the
Memory Map. Once set, it remains high until it is cleared by setting it to 1.
When set to 1 it indicates that the HDCP/EDID controller has reported an error. This error is available in
HDCP_CONTROLLER_ERROR. Once set, it remains high until it is cleared by setting it to 1.

Table 54: Status Bits in Main Map Register 0xEC42

Bit Position Description
6
See description for
5
See description for
Register Name Default Value
spare2_pb20[7:0] 0b00000000
spare2_pb21[7:0] 0b00000000
spare2_pb22[7:0] 0b00000000
spare2_pb23[7:0] 0b00000000
spare2_pb24[7:0] 0b00000000
spare2_pb25[7:0] 0b00000000
spare2_pb26[7:0] 0b00000000
spare2_pb27[7:0] 0b00000000
hpd_state
rx_sense_state
hdcp_controller_state[3:0]
252
Byte Name
Data Byte 20
Data Byte 21
Data Byte 22
Data Byte 23
Data Byte 24
Data Byte 25
Data Byte 26
Data Byte 27
on page 246
on page 247
status field.
ADV8003 Hardware Manual