Osd Scaler; Osd Master/Slave Spi Interface - Analog Devices ADV8003 Hardware Manual

timer1_irq_cnt[31:0], SPI Device Address 0x0B (TIMER), Address 0x4A[7:0]; Address 0x4B[7:0]; Address 0x4C[7:0]; Address 0x4D[7:0]
(Read Only)
The number of times the timer 1 interrupt was generated.
timer2_irq_cnt[31:0], SPI Device Address 0x0B (TIMER), Address 0x4E[7:0]; Address 0x4F[7:0]; Address 0x50[7:0]; Address 0x51[7:0]
(Read Only)
The number of times the timer 2 interrupt was generated.
timer3_irq_cnt[31:0], SPI Device Address 0x0B (TIMER), Address 0x52[7:0]; Address 0x53[7:0]; Address 0x54[7:0]; Address 0x55[7:0]
(Read Only)
The number of times the timer 3 interrupt was generated.
timer4_irq_cnt[31:0], SPI Device Address 0x0B (TIMER), Address 0x56[7:0]; Address 0x57[7:0]; Address 0x58[7:0]; Address 0x59[7:0]
(Read Only)
The number of times the timer 4 interrupt was generated.
timer5_irq_cnt[31:0], SPI Device Address 0x0B (TIMER), Address 0x5A[7:0]; Address 0x5B[7:0]; Address 0x5C[7:0]; Address 0x5D[7:0]
(Read Only)
The number of times the timer 5 interrupt was generated.
timer6_irq_cnt[31:0], SPI Device Address 0x0B (TIMER), Address 0x5E[7:0]; Address 0x5F[7:0]; Address 0x60[7:0]; Address 0x61[7:0]
(Read Only)
The number of times the timer 6 interrupt was generated.
timer7_irq_cnt[31:0], SPI Device Address 0x0B (TIMER), Address 0x62[7:0]; Address 0x63[7:0]; Address 0x64[7:0]; Address 0x65[7:0]
(Read Only)
The number of times the timer 7 interrupt was generated.
timer8_irq_cnt[31:0], SPI Device Address 0x0B (TIMER), Address 0x66[7:0]; Address 0x67[7:0]; Address 0x68[7:0]; Address 0x69[7:0]
(Read Only)
The number of times the timer 8 interrupt was generated.
4.2.7.

OSD Scaler

The ADV8003 OSD core contains an arbitrary resolution conversion scaler. This scaler performs a scaling function if the OSD resolution
inside the DDR2 memory is different from the output video. If the output video is interlaced, the OSD scaler can change the progressive
OSD data to interlaced data for blending. As mentioned in
OSD data and input video data.
4.2.8.

OSD Master/Slave SPI Interface

The ADV8003 OSD requires an external DDR2 memory and some configuration done to the OSD SPI registers in order to work. OSD
data can be written to the DDR2 memory on startup by the ADV8003. In addition, to dynamically configure the OSD, configuration
registers need to be controlled. Note that all this configuration is taken care of by Blimp OSD and the firmware, so a detailed explanation
of the DDR2 SPI interface is not provided. For this reason, this section covers only top level information (enable/disable, muxing
Rev. B, August 2013
Section 4.2.3, the OSD scaler also guarantees the correct synchronization of
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ADV8003 Hardware Manual