Table 59: Valid Configuration For Audio_Mode[1:0]; Table 60: Audio Input Format Summary - Analog Devices ADV8003 Hardware Manual

Function
mclk_ratio[1:0]
00
01 
10
11
mclk_en, TX2 Main Map, Address 0xF40B[5]
This bit is used to select the audio master clock that is used by the audio block.
Function
mclk_en
0 
1
audio_input_sel Value
0b010
0b011
audio_input audio_mode
_sel Value
Value
0b000 0bXX
0b000 0bXX
0b000 0bXX
0b000 0bXX
0b001 0b00
0b010 0b1X
0b010 0b1X
Rev. B, August 2013
Description
128*fs
256*fs
384*fs
512*fs
Description
Use internally generated MCLK
Use external MCLK
Table 59: Valid Configuration for
audio_mode Value
Options
0b0x
0b1x
0b00
0b01
0b10
0b11

Table 60: Audio Input Format Summary

Input
I2s_format Audio
Input
Value
Signal
0b00 I2S[3:0]
0b01 I2S[3:0]
0b10 I2S[3:0]
0b11 I2S[3:0]
0bXX SPDIF
0bXX DSD[5:0]
0bXX DSD[5:0]]
audio_mode[1:0]
Corresponding Configuration
DSD in raw mode
DSD in SDIF-3 mode
HBR input as 4 streams, with Bi-Phase Mark (BPM) encoding
HBR input as 4 stream, without BPM encoding
HBR input as 4 stream, without BPM encoding
HBR input as 1 stream, without BPM encoding
Clock Pins Encoding
SCLK, Normal
LRCLK,
MCLK
1
SCLK, Normal
LRCLK,
MCLK 1
SCLK, Normal
LRCLK,
MCLK
1
SCLK, Normal
LRCLK,
MCLK 1
MCLK 1 Biphase
Mark
SCLK Normal
SCLK SDIF-3
262
ADV8003 Hardware Manual
ADV8003 Format
Output Pin
Mapping
AUD_IN[4:0] Standard
I2S
AUD_IN[5]
SCLK
MCLK
AUD_IN[4:0] Right
justified
AUD_IN[5]
SCLK
MCLK
AUD_IN[4:0] Left justified
AUD_IN[5]
SCLK
MCLK
AUD_IN[4:0] AES3 direct
AUD_IN[5]
SCLK
MCLK
AUD_IN[0] IEC60958 or
IEC61937
MCLK
AUD_IN[5:0] DSD
SCLK
AUD_IN[5:0] DSD
SCLK
Output
Packet Type
Audio
Sample
Packet
Audio
Sample
Packet
Audio
Sample
Packet
Audio
Sample
Packet
Audio
Sample
Packet
DSD Packet
DSD Packet