Analog Devices ADV8003 Hardware Manual page 31

Video signal processor with motion adaptive deinterlacing, scaling, bitmap osd, dual hdmi tx and video encoder
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Pin
Mnemonic
No.
W21
PVDD6
W22
AVDD3
W23
NC
Y1
P[0]
Y2
P[1]
Y3
DDR_DQS[2]
Y4
GND
Y5
DDR_DQ[23]
Y6
DVDD_DDR
Y7
DDR_DQS[3]
Y8
GND
Y9
DDR_A[11]
Y10
DVDD_DDR
Y11
DDR_A[4]
Y12
GND
Y13
DDR_CAS
Y14
DVDD_DDR
Y15
DDR_ CK
Y16
GND
Y17
DDR_DQ[9]
Y18
DVDD_DDR
Y19
DDR_DQ[14]
Y20
GND
Y21
DDR_DQ[6]
Y22
PVDD_DDR
Y23
GND
AA1
DDR_DQ[18]
AA2
GND
AA3
GND
AA4
DDR_DQS[2]
AA5
DDR_DQ[26]
AA6
DVDD_DDR
AA7
DDR_DQS[3]
AA8
NC/GND
AA9
DDR_A[8]
AA10
DVDD_DDR
AA11
DDR_A[2]
AA12
GND
AA13
DDR_ CS
AA14
DVDD_DDR
AA15
DDR_CK
AA16
GND
AA17
DDR_DQ[11]
AA18
DVDD_DDR
AA19
DDR_DM[1]
Rev. B, August 2013
Type
Description
digital
Power
HDMI Tx PLL Power Supply (1.8 V). This pin is a voltage regulator output. Connect a
1
decoupling capacitor between this pin and ground.
Power
HDMI Analog Power Supply (1.8 V).
No connect
Do not connect to this pin.
Digital video input
Digital Video Input Bus[35:0].
Digital video input
Digital Video Input Bus[35:0].
DDR interface
Data Strobe for DDR Data Byte[23:16].
GND
Ground.
DDR interface
Data Line. Interface to external RAM data lines.
Power
DDR Interface Supply (1.8 V).
DDR interface
Data Strobe for DDR Data Byte[31:24].
GND
Ground.
DDR interface
Address Line. Interface to external RAM address lines.
Power
DDR Interface Supply (1.8 V).
DDR interface
Address Line. Interface to external RAM address lines.
GND
Ground.
DDR interface
Column Address Strobe for DDR Memory.
Power
DDR Interface Supply (1.8 V).
DDR interface
DDR Memory Clock. Interface to external DDR RAM clock lines.
GND
Ground.
DDR Interface
Data Line. Interface to external RAM data lines.
Power
DDR Interface Supply (1.8 V).
DDR interface
Data Line. Interface to external RAM data lines.
GND
Ground.
DDR interface
Data Line. Interface to external RAM data lines.
Power
DDR Interface PLL Supply (1.8 V).
GND
Ground.
DDR interface
Data Line. Interface to external RAM data lines.
GND
Ground.
GND
Ground.
DDR interface
Data Strobe for DDR Data Byte[23:16].
DDR interface
Data Line. Interface to external RAM data lines.
Power
DDR Interface Supply (1.8 V).
DDR interface
Data Strobe for DDR Data Byte[31:24].
No connect/GND
For new ADV8003 designs, do not connect to this pin. For designs that must
maintain consistency with the ADV8002, this pin can be grounded.
DDR interface
Address Line. Interface to external RAM address lines.
Power
DDR Interface Supply (1.8 V).
DDR interface
Address Line. Interface to external RAM address lines.
GND
Ground.
DDR interface
DDR Chip Select. Interface to external DDR RAM chip selects.
Power
DDR Interface Supply (1.8 V).
DDR interface
DDR Memory Clock. Interface to external DDR RAM clock lines.
GND
Ground.
DDR interface
Data Line. Interface to external RAM data lines.
Power
DDR Interface Supply (1.8 V).
DDR interface
Data Mask for Data Lines[15:8].
31
ADV8003 Hardware Manual

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