Spi Loop Through; Vbi Data Insertion; Extraction Overview - Analog Devices ADV8003 Hardware Manual

Video signal processor with motion adaptive deinterlacing, scaling, bitmap osd, dual hdmi tx and video encoder
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ADV8003. By default, this is set to 1 which means that a read from a particular address in the ADV8003 increments the read pointer to
the next register map address.
read_auto_inc_en, IO Map, Address 0x1AFC[0]
This register is used to auto increment I2C addresses in the device for consecutive reads.
Function
read_auto_inc_en
0
1 
2.2.7.

SPI Loop Through

The ADV8003 SPI ports can be put in loop through mode for programming the external SPI flash that may be connected to the ADV8003
master SPI port (if an OSD design is to be used). Refer to Section 4.2.8 for more information.
spi_loop_through, IO Map, Address 0x1AB6[5]
This bit is used to enable SPI loop through mode.
Function
spi_loop_through
0 
1
2.2.8.

VBI Data Insertion

ADV8003 supports VBI data (such as CGMS, WSS, and CCAP) insertion into the video stream through either the ancillary data input (Y
channel input of 36-bit data bus) or the SPI-compatible slave input (VBI_SCK, VBI_MOSI and VBI_CS). When using the SPI-compatible
slave input for VBI insertion, a reduced set of video input formats are supported on the EXOSD TTL input due to the shared pins. The
VBI data is decoded and supplied to the encoder for output in the video data stream.
The supported VBI standards are the following:
WSS (625i)
CCAP (525i and 625i)
CGMS (525i)
CGMS (525p)
CGMS (625p)

2.2.8.1. Extraction Overview

VBI data can be supplied to the ADV8003 through two separate interfaces. If there is a pixel bus input from the front end decoder then
the VBI data may be provided via an ancillary data stream encoded into the video data. If a pixel bus is not available, the VBI data can be
sent via the dedicated SPI interface. Refer to
Rev. B, August 2013
Description
No auto increment of I2C address for consecutive reads
Auto increment of I2C address for consecutive reads
Description
Regular SPI mode
SPI slave clock routed to SPI master clock output
Figure 44
for an overview of this architecture.
119
ADV8003 Hardware Manual

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