Audio Configuration - Analog Devices ADV8003 Hardware Manual

AUD_IN[5]

6.11.2. Audio Configuration

The audio_input_sel[2:0],
audio input. Refer to Figure 89
audio_input_sel[2:0], TX2 Main Map, Address 0xF40A[6:4]
This signal is used to select the input format of the audio.
Function
audio_input_sel[2:0]
000 
001
010
011
100
i2s_format[1:0], TX2 Main Map, Address 0xF40C[1:0]
This signal is used to set the format of the I2S audio stream input to the part.
Function
i2s_format[1:0]
00 
01
10
11
audio_mode[1:0], TX2 Main Map, Address 0xF40A[3:2]
Mode Selection for Audio Select Case 1: DSD (AUDIO_SLECT = 0b010): 0x = DSD raw mode 1x = SDIF-3 mode Case 2: HBR
(AUDIO_SLECT = 0b011): 00 = 4 stream, with Bi-Phase Mark (BPM) encoding 01 = 4 stream, without BPM encoding 10 = 1 stream,
with BPM encoding 11 = 1 stream, without BPM encoding
Function
audio_mode[1:0]
00 
01
10
11
mclk_ratio[1:0], TX2 Main Map, Address 0xF40A[1:0]
This signal is used to specify the ratio between the audio sampling frequency and the clock described using the N and CTS values.
Rev. B, August 2013
DSD.5/LRCLK DSD.5/LRCLK
audio_mode[1:0], and i2s_format[1:0]
to Figure 95 for more information on the audio timing formats.
Description
I2S
SPDIF
One Bit Audio (DSD)
High Bit Rate (HBR) Audio
Reserved
Description
I2S
Right justified
Left justified
AES3 direct mode
Description
See description
See description
See description
See description
LRCLK
fields must be used to configure the Tx core according to the incoming
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ADV8003 Hardware Manual
LRCLK SPDIF