Table 43: Isrc2 Packet Registers - Analog Devices ADV8003 Hardware Manual

1 As defined by the HDMI 1.4 specifications
The ISRC1 packet registers are considered valid if
isrc1_pckt_raw, IO, Address 0x60[6] (Read Only)
This read-back indicates the raw status signal of the International Standard Recording Code 1 (ISRC1) packet detection signal. This bit
resets to 0 after an HDMI packet detection reset or upon writing to isrc1_packet_id.
Function
isrc1_pckt_raw
0 
1
InfoFrame
Map Address
0xE3F5
0x E3F6
0x E3F7
0x E3A8
0x E3A9
0x E3AA
0x E3AB
0x E3AC
0x E3AD
0x E3AE
0x E3AF
0x E3B0
0x E3B1
0x E3B2
0x E3B3
0x E3B4
0x E3B5
0x E3B6
0x E3B7
Rev. B, August 2013
InfoFrame R/W
Map Address
0x9B R
0x9C R
0x9D R
0x9E R
0x9F R
0xA0 R
0xA1 R
0xA2 R
0xA3 R
0xA4 R
0xA5 R
0xA6 R
0xA7 R
rx_isrc1_pckt_edge_raw
Description
No ISRC1 packets received since last HDMI packet detection reset.
ISRC1 packets received.

Table 43: ISRC2 Packet Registers

R/W Register Name
R/W isrc2_packet_id[7:0]
R isrc2_header1
R isrc2_header2
R isrc2_pb_0_1
R isrc2_pb_0_2
R isrc2_pb_0_3
R isrc2_pb_0_4
R isrc2_pb_0_5
R isrc2_pb_0_6
R isrc2_pb_0_7
R isrc2_pb_0_8
R isrc2_pb_0_9
R isrc2_pb_0_10
R isrc2_pb_0_11
R isrc2_pb_0_12
R isrc2_pb_0_13
R isrc2_pb_0_14
R isrc2_pb_0_15
R isrc2_pb_0_16
Register Name
isrc1_pb_0_16
isrc1_pb_0_17
isrc1_pb_0_18
isrc1_pb_0_19
isrc1_pb_0_20
isrc1_pb_0_21
isrc1_pb_0_22
isrc1_pb_0_23
isrc1_pb_0_24
isrc1_pb_0_25
isrc1_pb_0_26
isrc1_pb_0_27
isrc1_pb_0_28
is set to 1.
240
ADV8003 Hardware Manual
Packet Byte No.
1
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
Packet Byte No.
1
Packet Type Value
HB1
HB2
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15