Autoconfiguration - Analog Devices ADV8005 Hardware Reference Manual

ADV8005 Hardware Reference Manual
pvsp_bypass, Primary VSP Map, Address 0xE829[7]
This bit is used to bypass the Primary VSP. If this bit is set to 1, the input video to the Primary VSP will be directly bypassed to the output port.
Function
pvsp_bypass
0 (default)
1
The VIM and VOM must be enabled if using the PVSP. This can be done by enabling the
must be done regardless of the video conversions being performed.
pvsp_enable_vim, Primary VSP Map, Address 0xE828[1]
This bit is used to control the Video Input Module (VIM). If this bit is set to 1, the VIM is enabled to write packed input video data into a
defined external field/frame buffer. While the Primary VSP is running, if this bit is set to 0, the output video stream will be frozen.
Function
pvsp_enable_vim
0 (default)
1
pvsp_enable_vom, Primary VSP Map, Address 0xE828[2]
This bit is used to control the Video Output Module (VOM). If this bit is set to 1, the VOM is enabled to read video data from external
memory, process it and then output it.
Function
pvsp_enable_vom
0 (default)
1
Also, if using the PVSP, the FFS must be enabled using pvsp_enable_ffs. This informs the hardware of the various conversions that must be
performed. Field/frame buffers in external memory are managed by the FFS which decides which field/frame buffer should be used by the VIM
to store input video data. The FFS also decides which field/frame buffer should be read back by VOM to process. In the case of interlaced video,
the FFS informs the VOM if the input video is the even field or the odd field. The PVSP utilizes a frame repeat/drop mechanism to implement
FRC, which is also managed by the FFS.
pvsp_enable_ffs, Primary VSP Map, Address 0xE828[0]
This bit is used to control the Field Frame Scheduler (FFS). If this bit is set to 1, the FFS is enabled and the VIM and VOM are scheduled by
the FFS, which means the Primary VSP is in operating mode. If this bit is set to 0, the Primary VSP is in idle mode.
Function
pvsp_enable_ffs
0 (default)
1
3.2.1.1.

Autoconfiguration

Each block inside VIM and VOM can be automatically configured to reduce the configuration complexity. Two registers,
pvsp_autocfg_input_vid[7:0]
The 59.94/23.97 Hz timings have the same VID as the corresponding 60/24Hz timing in
pvsp_autocfg_input_vid[7:0], Primary VSP Map, Address 0xE881[7:0]
This register is used to set the input timing VIC. If this register is 0, PVSP will use values in registers of pvsp_vin_h, pvsp_vin_v,
pvsp_is_i_to_p and pvsp_vin_fr to set input video.
Function
pvsp_autocfg_input_vid[7:0]
0x06 (default)
0xXX
Description
Not bypass Primary VSP
Bypass Primary VSP
Description
Disable VIM
Enable VIM
Description
Disable VOM
Enable VOM
Description
Disable FFS/FRC
Enable FFS/FRC
and pvsp_autocfg_output_vid[7:0]
Description
Default: 480i@60
Input timing VID
should be set to make the auto configuration work.
Figure
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pvsp_enable_vim and pvsp_enable_vom
20.
UG-707
bits. This