Tpui Formatter - ST STM32F413 Reference Manual

RM0430
Note: By default, the TRACECLKIN input clock of the TPIU is tied to GND. It is assigned to HCLK
two clock cycles after the bit TRACE_IOEN has been set.
The debugger must then program the Trace Mode by writing the PROTOCOL[1:0] bits in the
SPP_R (Selected Pin Protocol) register of the TPIU.
•
PROTOCOL=00: Trace Port Mode (synchronous)
•
PROTOCOL=01 or 10: Serial Wire (Manchester or NRZ) Mode (asynchronous mode).
Default state is 01
It then also configures the TRACE port size by writing the bits [3:0] in the CPSPS_R
(Current Sync Port Size Register) of the TPIU:
•
0x1 for 1 pin (default state)
• 0x2 for 2 pins
•
0x8 for 4 pins
34.17.3

TPUI formatter

The formatter protocol outputs data in 16-byte frames:
•
seven bytes of data
•
eight bytes of mixed-use bytes consisting of:
–
–
•
one byte of auxiliary bits where each bit corresponds to one of the eight mixed-use
bytes:
–
–
Note: Refer to the ARM
information
34.17.4 TPUI frame synchronization packets
The TPUI can generate two types of synchronization packets:
• The Frame Synchronization packet (or Full Word Synchronization packet)
It consists of the word: 0x7F_FF_FF_FF (LSB emitted first). This sequence can not
occur at any other time provided that the ID source code 0x7F has not been used.
It is output periodically between frames.
In continuous mode, the TPA must discard all these frames once a synchronization
frame has been found.
•
The Half-Word Synchronization packet
It consists of the half word: 0x7F_FF (LSB emitted first).
It is output periodically between or within frames.
These packets are only generated in continuous mode and enable the TPA to detect
that the TRACE port is in IDLE mode (no TRACE to be captured). When detected by
the TPA, it must be discarded.
1 bit (LSB) to indicate it is a DATA byte ('0) or an ID byte ('1).
7 bits (MSB) which can be data or change of source ID trace.
if the corresponding byte was a data, this bit gives bit0 of the data.
if the corresponding byte was an ID change, this bit indicates when that ID change
takes effect.
®
CoreSight Architecture Specification v1.0 (ARM
DocID029473 Rev 3
Debug support (DBG)
®
IHI 0029B) for further
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