Periods In Which Interrupts Are Not Acknowledged - NEC V850E/MA1 User Manual

CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION

7.8 Periods in Which Interrupts Are Not Acknowledged

An interrupt is acknowledged while an instruction is being executed. However, no interrupt will be acknowledged
between an interrupt request non-sample instruction and the next instruction (interrupt is held pending).
The interrupt request non-sample instructions are as follows.
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instruction (for PSW)
• The store instruction for the command register (PRCMD)
• The load, store, or bit manipulation instructions for the following registers.
• Interrupt-related registers:
Interrupt control register (xxICn), interrupt mask registers 0 to 3 (IMR0 to IMR3),
in-service priority register (ISPR)
• CSI-related registers:
Clocked serial interface clock selection registers 0 to 2 (CSIC0 to CSIC2),
clocked serial interface mode registers 0 to 2 (CSIM0 to CSIM2),
serial I/O shift registers 0 to 2 (SIO0 to SIO2),
receive-only serial I/O shift registers 0 to 2 (SIOE0 to SIOE2),
clocked serial interface transmit buffer registers 0 to 2 (SOTB0 to SOTB2)
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