Interrupt Latency Time; Periods Where Interrupt Is Not Acknowledged - NEC V850/SA1 mPD703015 Preliminary User's Manual

5.7 Interrupt Latency Time

The following table describes the V850/SA1 interrupt latency time (from interrupt request generation to start of in-
terrupt processing).
Figure 5-17. Pipeline Operation at Interrupt Request Acknowledge
System clock
Interrupt request
Instruction 1
Instruction 2
Instruction 3
Interrupt acknowledge operation
Instruction (start instruction of
interrupt processing routine)
INT1 to INT4: interrupt acknowledge processing
IFx : invalid instruction fetch
IDx : invalid instruction decode
Interrupt Latency Time (system clock)
Internal interrupt
Minimum 11
Maximum 18

5.8 Periods Where Interrupt is Not Acknowledged

An interrupt is acknowledged while an instruction is being executed. However, no interrupt will be acknowledged
between interrupt non-sample instruction and next instruction.
Interrupt request non-sample instruction
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instruction (vs. PSW)
130
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
7 to 14 system clocks
External interrupt
13
20
4 system clocks
IF ID EX MEM WB
IFx IDx
IFx
INT1 INT2 INT3
IF
Condition
Time to eliminate noise (2 system clocks) is also necessary
for external interrupts, except when:
• In IDLE/STOP mode
• External bus is accessed
• Two or more interrupt request non-sample instructions
are executed in succession
• Access to interrupt control register
INT4
ID EX MEM WB