Periods In Which Interrupts Are Not Acknowledged; Interrupt Request Valid Timing Following Ei Instruction - NEC Renesas V850/SC1 User Manual

7.8 Periods in Which Interrupts Are Not Acknowledged

Interrupts are acknowledged while an instruction is being executed. However, no interrupt will be acknowledged
between an interrupt request non-sample instruction and the next instruction.
Interrupt request non-sample instruction
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instruction (vs. PSW)

7.8.1 Interrupt request valid timing following EI instruction

When an interrupt request is generated (IF flag = 1) in the status in which interrupts have been disabled by the DI
instruction and interrupts are not masked (MK flag = 0), 7 system clocks are required until the interrupt request is
acknowledged following execution of the EI instruction (interrupt enable). If the DI instruction (interrupt disable) is
executed during the 7 system clocks, the interrupt request is not acknowledged by the CPU.
Therefore, instructions equivalent to 7 system clocks must be inserted as the number of instruction execution
clocks after executing the EI instruction (interrupt enable). However, securing 7 system clocks is disabled under the
following conditions because an interrupt request is not acknowledged even if 7 system clocks are secured.
• IDLE/STOP mode
• Interrupt request non-sampling instruction (instruction to manipulate PSD.ID bit)
• Access to interrupt request control register (xxICn)
The following shows an example of program processing.
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User's Manual U15109EJ3V0UD