Periods In Which Interrupts Are Not Acknowledged By Cpu - NEC V850ES/SA2 UPD703201 Manual

14.7 Periods in Which Interrupts Are Not Acknowledged by CPU

An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be
acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending).
The interrupt request non-sample instructions are as follows.
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instruction (for PSW)
• The store instruction for the command register (PRCMD)
• The load, store, or bit manipulation instructions for the following interrupt-related registers.
Interrupt control register (xxICn), interrupt mask registers 0 to 2 (IMR0 to IMR2), in-service priority register
(ISPR)
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Preliminary User's Manual U15905EJ1V0UD
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