One-Shot Pulse Mode (Taanmd2 To Taanmd0 = 011 B ) - NEC V850ES/F 3-L Series User Manual

Chapter 10
10.6.5 One-shot pulse mode (TAAnMD2 to TAAnMD0 = 011
Caution
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When TAAnCE is set to 1 in the one-shot pulse mode, the 16-bit counter waits
for the setting of the TAAnEST bit (to 1) or a trigger that is input when the edge
of the TIAAn0 pin is detected, while holding FFFFH. When the trigger is input,
the 16-bit counter starts counting up.
When the value of the 16-bit counter matches the value of the CCR1 buffer
register that has been transferred from the TAAnCCR1 register, TOAAn1 goes
high. When the value of the 16-bit counter matches the value of the CCR0
buffer register that has been transferred from the TAAnCCR0 register, TOAAn1
goes low, and the 16-bit counter is cleared to 0000H and stops. Input of a
second or subsequent trigger is ignored while the 16-bit counter is operating.
Be sure to input a second trigger while the 16-bit counter is stopped at 0000H.
In the one shot pulse mode, rewriting the TAAnCCR0 and TAAnCCR1 registers
is enabled when TAAnCE = 1. The set values of the TAAnCCR0 and
TAAnCCR1 registers become valid after a write instruction from the CPU is
executed. They are then transferred to the CCR0 and CCR1 buffer registers,
and compared with the value of the 16-bit counter. The waveform of the one-
shot pulse is output from the TOAAn1 pin. The TOAAn0 pin produces a toggle
output when the value of the 16-bit counter matches the value of the
TAAnCCR0 register. In the one-shot pulse mode, the TAAnCCR0 and
TAAnCCR1 registers function only as compare registers. They cannot be used
as capture registers.
1. In the one-shot pulse mode, select the internal clock (TAAnEEE bit of
TAAnCTL1 register = 0) as the count clock.
2. In the one-shot pulse mode, it is prohibited to set the TAAnCCR1 register to
0000H.
User's Manual U18743EE1V2UM00
16-Bit Timer/Event Counter AA
B
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