Erase Block Register 1 (Ebr1) - Hitachi H8/3664 Hardware Manual

Bit 7: FLER
0
1
Bits 6 to 0—Reserved: These bits always read 0.
7.3.3

Erase Block Register 1 (EBR1)

EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a power-on reset, or in standby mode, or when the SWE bit in FLMCR1 is 0.
When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-
protected. Do not set more than one bit, as this will cause all the bits in EBR1 to be automatically
cleared to 0.
The flash memory erase blocks are shown in table 7.3.
Bit 7
—
Initial value 0
Read/Write R/W
Table 7.3 Flash Memory Erase Blocks
Block (Size)
EB0 (1 kbyte)
EB1 (1 kbyte)
EB2 (1 kbyte)
EB3 (1 kbyte)
EB4 (28 kbytes)
Description
Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Power-on reset or standby mode
An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 7.7.3, Error Protection
6
—
0
R/W R/W
Addresses
H'0000–H'03FF
H'0400–H'07FF
H'0800–H'0BFF
H'0C00–H'0FFF
H'1000–H'7FFF
5 4
— EB4
0 0
R/W
3 2
EB3 EB2
0 0
R/W R/W
(Initial value)
1 0
EB1 EB0
0 0
R/W R/W
107