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Bit
Bit Name
2
CH2
1
CH1
0
CH0
14.3.3
A/D Control Register (ADCR)
The ADCR enables A/D conversion started by an external trigger signal.
Bit
Bit Name
7
TRGE
6
—
5
—
4
—
3
—
2
—
1
—
0
—
Rev. 1.0, 03/01, page 198 of 280
Initial Value
R/W
0
R/W
0
R/W
0
R/W
Initial Value
R/W
0
R/W
1
—
1
—
1
—
1
—
1
—
1
—
0
R/W
Description
Channel Select 0 to 2
Select analog input channels.
When SCAN = 0
000: AN0
001: AN1
010: AN2
011: AN3
Description
Trigger Enable
A/D conversion is started at the falling edge and
the rising edge of the external trigger signal
(ADTRG) when this bit is set to 1.
The selection between the falling edge and rising
edge of the external trigger pin (ADTRG) comforms
to the WPEG5 bit in the interrupt edge select
register 2(IEGR2)
Reserved
These bits are always read as 1 and cannot be
modified.
Reserved
Do not set this bit to 1, though the bit is
readable/writable.
When SCAN = 1
000: AN0
001: AN0 to AN1
010: AN0 to AN2
011: AN0 to AN3
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