A/D Control Register (Adcr)-H'ffea - Hitachi H8/329 Series Hardware Manual

9.2.3 A/D Control Register (ADCR)—H'FFEA
Bit 7
TRGE
Initial value 0
Read/Write R/W
The A/D control register (ADCR) is an 8-bit readable/writable register that enables or disables the
A/D external trigger signal.
The ADCR is initialized to H'7E at a reset and in the standby modes.
Bit 7—Trigger Enable (TRGE): This bit enables the ADTRG (A/D external trigger) signal to set
the ADST bit and start A/D conversion.
Bit 7
TRGE Description
0 A/D external trigger is disabled. ADTRG does not set
the ADST bit.
1 A/D external trigger is enabled. ADTRG sets the ADST bit.
(The ADST bit can also be set by software.)
Bits 6 to 1—Reserved: These bits cannot be modified and are always read as "1."
Bit 0—Channel Set Select (CHS): This bit is reserved. It does not affect the operation of the
chip.
6 5 4
— — —
1 1 1
— — —
215
3 2 1
— — —
1 1 1
— — —
0
CHS
0
R/W
(Initial value)