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3.4 Operating Mode Descriptions
3.4.1 Mode 1
Ports 1, 2, and 5 function as address pins A
to A
, permitting access to a maximum 1-Mbyte
19
0
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas.
3.4.2 Mode 3
Ports 1, 2, and 5 and part of port A function as address pins A
to A
, permitting access to a
23
0
maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to
all areas. A
to A
are valid when 0 is written in bits 7 to 5 of the bus release control register
23
21
(BRCR). (In this mode A
is always used for address output.)
20
3.4.3 Mode 5
Ports 1, 2, and 5 can function as address pins A
to A
, permitting access to a maximum 1-Mbyte
19
0
address space, but following a reset they are input ports. To use ports 1, 2, and 5 as an address bus,
the corresponding bits in their data direction registers (P1DDR, P2DDR, and P5DDR) must be set
to 1. The address bus width can be selected freely by setting DDR of ports 1, 2, and 5. The initial
bus mode after a reset is 8 bits, with 8-bit access to all areas.
3.4.4 Mode 6
This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available.
Mode 6 is a normal mode with 64-kbyte address space.
3.4.5 Mode 7
This mode is an advanced mode with a 1-Mbyte address space which operates using the on-chip
ROM, RAM, and registers. All I/O ports are available.
Note: The H8/3039 Series cannot be used in mode 2 and 4.
60
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