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3.4 Operating Mode Descriptions
3.4.1 Mode 1
Ports 1, 2, and 5 function as address pins A
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas.
3.4.2 Mode 3
Ports 1, 2, and 5 and part of port A function as address pins A
maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to
all areas. A
to A
23
21
(BRCR). (In this mode A
3.4.3 Mode 5
Ports 1, 2, and 5 can function as address pins A
address space, but following a reset they are input ports. To use ports 1, 2, and 5 as an address bus,
the corresponding bits in their data direction registers (P1DDR, P2DDR, and P5DDR) must be set
to 1. The address bus width can be selected freely by setting DDR of ports 1, 2, and 5. The initial
bus mode after a reset is 8 bits, with 8-bit access to all areas.
3.4.4 Mode 6
Ports 1, 2, and 5, and port A (PA
maximum 16-Mbyte address space, but following a reset these pins, except for A
To use ports 1, 2, and 5 as address bus pins A
registers (P1DDR, P2DDR, and P5DDR) must be set to 1 to select output mode. A
enabled by writing 0 to bits 7 to 5 in the address control register (ADRCR). The address bus
width can be selected freely (excluding A
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas.
3.4.5 Mode 7
This mode is an advanced mode with a 1-Mbyte address space which operates using the on-chip
ROM, RAM, and registers. All I/O ports are available.
Note: The H8/3022 Series cannot be used in mode 2 and 4.
60
are valid when 0 is written in bits 7 to 5 of the bus release control register
is always used for address output.)
20
to PA
7
to A
, permitting access to a maximum 1-Mbyte
19
0
to A
, permitting access to a maximum 1-Mbyte
19
0
) function as address pins A
4
to A
, the corresponding bits in their data direction
19
0
) by setting DDR of ports 1, 2, and 5, and ADRCR.
20
to A
, permitting access to a
23
0
to A
, permitting access to a
23
0
20
, are input ports.
to A
are
23
21
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