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PREPARATION FOR USE
2-23.
8251A PCI and Serial Interface Jumper Configurations
The 8251A Programmable Communications Interface (PCI) device contains
jumper posts for configuration of the Transmit Clock (TxC), the Receive
Clock (RxC), the Clear-To-Send (CTS), the Data Terminal Ready (DTR), and
the Data Set Ready (DSR) inputs.
The TxC signal may be derived from one of two sources:
either from the
Secondary Transmit Clock input signal from the RS232C interface via
E186-E190 or from the OUT2 clock from the PIT device via E190-E194 (the
as shipped configuration).
The RxC signal may be derived from one of two sources:
either from the
Secondary Transmit Clock input signal from the RS232C interface via
E187-E191 or from the OUT2 clock from the PIT device via E191-E195 (the
as shipped configuration).
The DTR signal from the RS232C interface contains a jumper option
E189-E193.
The jumper allows user selection of the source signal for
generating the Data Set Ready input to the PCI device.
Available sources
are the Request-To-Send signal (RTS), configured via E76-E193, and
ground, configured via E62-E193.
The iSBC 86/14/30 board contains several jumper options for configuring
the operation of RS232C signals on the serial interface.
Signals that
may be configured include the Request-To-Send input (E76), the
Clear-To-Send output (E77), the Transmit Signal Element Timing output
(E80), the Secondary Receive output (E78), and the Secondary
Clear-To-Send output (E81).
The as-shipped configuration of the iSBC
86/14/30 board contains no jumpers on these signals.
2-24.
Failsafe Timer Jumper Configuration
The iSBC 86/14/30 board contains one jumper option for configuration of
the Failsafe Timer feature of the board.
Jumper connection E38-E39
enables a bus timeout signal (TIME OUT INTR/) to input a timeout signal
to the READY input of the on-board 8086-2 CPU when an expected response
from another device (in the form of an XACK/ signal) is too late in
arriving at the iSBC 86/14/30 board.
A description of operation is
contained in paragraph 4-40.
As shipped, the iSBC 86/14/30 board contains a jumper connecting
E38-E39.
If you do not desire the use of the feature, remove the jumper.
2-25.
Status Register Jumper Configurations
The Status Register on the iSBC 86/14/30 board contains 8 programmable
functions, five of which are user configurable (three are dedicated).
The functions performed are as follows:
bit 0 is a user configurable
output that may be used to provide GATE control for Counter 0 of the
8253-5 PIT, bit 1 provides GATE control for Counter 1 of the 8253-5 PIT,
2-46
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