Second Level Cache; Chipset; 82439Tx System Controller (Mtxc) - Intel AN430TX - Motherboard - ATX Technical Product Specification

AN430TX Motherboard Technical Product Specification
1.6.1.2 SDRAM
Synchronous DRAM (SDRAM) is designed to improve main memory performance. Unlike fast
page or EDO DRAM, SDRAM is synchronous with the memory clock. This simplifies the timing
design and increases memory speed because all timing is dependent on the number of memory
clock cycles. SDRAM DIMM should meet the Intel 4-clock 66 MHz 64-bit unbuffered SDRAM
DIMM v1.0 specification.
CAUTION
The board does not support SDRAM DIMMs with an n x 4 DRAM base due to loading anomalies.
For example, a DIMM that uses sixteen 16 Mbit x 4 devices should not be used.
NOTE
The AN430TX supports unbuffered, 4-clock 3.3V SDRAM DIMMs only. Buffered, 5V, or 2-clock
SDRAM DIMMs cannot be used.

1.6.2 Second Level Cache

The 512 KB direct-mapped write-back L2 cache consists of two 64K x 32 global write enable
(GWE) pipeline burst asynchronous RAMs (PBSRAMs) and a 32K x 8 external tag SRAM. These
devices are soldered to the motherboard.

1.7 Chipset

The Intel 82430TX PCIset consists of the 82439TX System Controller (MTXC) device and the
82371AB PCI ISA IDE Xcelerator (PIIX4) device.

1.7.1 82439TX System Controller (MTXC)

The MTXC integrates the cache and main memory DRAM control functions and provides bus
control to handle transfers between the processor, cache, main memory, and the PCI bus. The
MTXC allows PCI masters to achieve full PCI bandwidth by using the snoop ahead feature. For
increased system performance the MTXC integrates posted write and read prefetch buffers. The
MTXC comes in a 324-pin MBGA package that features:
Microprocessor interface control
Integrated L2 write-back cache controller
Supports pipeline burst SRAM
64 MB maximum DRAM cacheability
Direct mapped organization—write back only
Cache hit read/write cycle timings at 3-1-1-1
Back to back read/write cycles at 3-1-1-1-1-1-1-1
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