Logic Elements And Logic Array Blocks; Analog-To-Digital Converter - Intel MAX 10 FPGA User Manual

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1 MAX 10 FPGA Device Overview
Table 7. Pin Migration Conditions for ADC Migration
Source
Single ADC device
Dual ADC device
Single ADC device
Dual ADC device

1.7 Logic Elements and Logic Array Blocks

The LAB consists of 16 logic elements (LE) and a LAB-wide control block. An LE is the
smallest unit of logic in the MAX 10 device architecture. Each LE has four inputs, a
four-input look-up table (LUT), a register, and output logic. The four-input LUT is a
function generator that can implement any function with four variables.
Figure 4. MAX 10 Device Family LEs
data 1
data 2
data 3
data 4

1.8 Analog-to-Digital Converter

MAX 10 devices feature up to two ADCs. You can use the ADCs to monitor many
different signals, including on-chip temperature.
Target
Single ADC device
Dual ADC device
Dual ADC device
Single ADC device
Register Chain
Routing from
previous LE
LE Carry-In
Look-Up Table Carry
(LUT) Chain
Chip-Wide
Register Feedback (DEV_CLRn)
LE Carry-Out
labclkena1
labclkena2
Migratable Pins
You can migrate all ADC input pins
• One dedicated analog input pin.
• Eight dual function pins from the ADC1 block of the
source device to the ADC1 block of the target device.
Register Bypass
LAB-Wide
LAB-Wide
Synchronous
Synchronous
Load
Clear
Synchronous
D
Load and
Clear Logic
ENA
CLRN
labclr1
labclr2
Asynchronous
Clear Logic
Reset
Clock &
Clock Enable
Select
labclk1
labclk2
Row, Column,
And Direct Link
Q
Routing
Row, Column,
And Direct Link
Routing
Local
Routing
Register Chain
Output
MAX 10 FPGA Device Overview
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