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R
6.2.2
System Memory 2-DIMM Layout Guidelines
Figure 43. System Memory 2-DIMM Routing Topologies
Topology 1
Topology 2
Topology 3
Topology 4
Topology 5
Table 19. System Memory 2-DIMM Solution Space
Signal
Top.
SCS[3:2]#
3
SCS[1:0]#
2
SMAA[7:4]
4
SMAB[7:4]#
5
SCKE[3:2]
3
SCKE[1:0]
2
SMD[63:0]
1
SDQM[7:0]
1
SCAS#, SRAS#, SWE#
1
SBS[1:0],
1
SMAA[12:8,3:0]
In addition to meeting the spacing requirements outlined in Table 19, system memory signal trace
edges must be at least 30 mils from any other non-system memory signal trace edge.
®
Intel
815EG Chipset Platform Design Guide
82815
10 Ω
E
10 Ω
E
Trace (mils)
A
Width
Spacing
Min.
Max.
5
10
5
10
10
10
10
10
10
10
10
10
5
10
1.75
10
10
1.5
3.5
5
10
1
4.0
5
10
1
4.0
System Memory Design Guidelines
A
C
D
F
F
Trace Lengths (inches)
B
C
Min.
Max.
Min.
Max.
1
4.5
3
4
4
0.4
0.5
0.4
0.5
0.4
0.5
0.4
0.5
DIMM 0
DIMM 1
B
sys_mem_2DIMM_routing_topo
D
E
Min.
Max.
Min.
Max.
Min.
1
4.5
0.4
0.5
2
0.4
0.5
2
3
4
F
Max.
4
4
79
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