Command Sequence Diagram - Motorola ColdFire MCF5281 User Manual

Background Debug Mode (BDM)
29.5.3.2 Command Sequence Diagrams
The command sequence diagram in Figure 29-16 shows serial bus traffic for commands.
Each bubble represents a 17-bit bus transfer. The top half of each bubble indicates the data
the development system sends to the debug module; the bottom half indicates the debug
module's response to the previous development system commands. Command and result
transactions overlap to minimize latency.
Commands transmitted to the debug module
Command code transmitted during this cycle
READ (LONG) MS ADDR
??? 'NOT READY'
'ILLEGAL'
Results from previous command
Responses from the debug module
The sequence is as follows:
• In cycle 1, the development system command is issued (
debug module responds with either the low-order results of the previous command
or a command complete status of the previous command, if no results are required.
• In cycle 2, the development system supplies the high-order 16 address bits. The
debug module returns a not-ready response unless the received command is decoded
as unimplemented, which is indicated by the illegal command encoding. If this
occurs, the development system should retransmit the command.
A not-ready response can be ignored except during a
memory-referencing cycle. Otherwise, the debug module can
accept a new serial transfer after 32 processor clock periods.
• In cycle 3, the development system supplies the low-order 16 address bits. The
debug module always returns a not-ready response.
29-22
High-order 16 bits of memory address
LS ADDR
'NOT READY'
XXX NEXT CMD
'NOT READY'
Data used from this transfer
Sequence taken if illegal command
is received by debug module
Figure 29-16. Command Sequence Diagram
MCF5282 User's Manual
Low-order 16 bits of memory address
Non-serial-related
activity
READ
MEMORY
LOCATION
NOTE:
Sequence taken if operation
has not completed
Next
Command
XXX
Code
'NOT READY'
XXX NEXT CMD
MS RESULT LS RESULT
XXX NEXT CMD
BERR 'NOT READY'
Sequence taken if bus error
occurs on memory access
High- and low-order 16 bits of result
in this example). The
READ
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