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Table 17-2. User Initialization (Before ECR[ETHER_EN]) (continued)
FEC FIFO/DMA registers that require initialization are defined in Table 17-3.
Table 17-3. FEC User Initialization (Before ECR[ETHER_EN])
17.4.3 Microcontroller Initialization
In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN]
is asserted. After the microcontroller initialization sequence is complete, the hardware is
ready for operation.
Table 17-4 shows microcontroller initialization operations.
17.4.4 User Initialization (After Asserting ECR[ETHER_EN])
After asserting ECR[ETHER_EN], the user can set up the buffer/frame descriptors and
write to the TDAR and RDAR. Refer to Section 17.6, "Buffer Descriptors" for more
details.
MOTOROLA
Description
MSCR (optional)
Clear MIB_RAM (locations IPSBAR + 0x1200-0x12FC)
Description
Initialize FRSR (optional)
Initialize EMRBR
Initialize ERDSR
Initialize ETDSR
Initialize (Empty) Transmit Descriptor ring
Initialize (Empty) Receive Descriptor ring
Table 17-4. Microcontroller Initialization
Description
Initialize BackOff Random Number Seed
Activate Receiver
Activate Transmitter
Clear Transmit FIFO
Clear Receive FIFO
Initialize Transmit Ring Pointer
Initialize Receive Ring Pointer
Initialize FIFO Count Registers
Chapter 17. Fast Ethernet Controller (FEC)
Functional Description
17-7
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