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Table 17-12. EIR Field Descriptions (continued)
Bits
28
27
26
25
24
23
22
21
20
19
18–0
MOTOROLA
Name
GRA
Graceful stop complete. This interrupt will be asserted for one of
three reasons. Graceful stop means that the transmitter is put into
a pause state after completion of the frame currently being
transmitted.
1) A graceful stop, which was initiated by the setting of the
TCR[GTS] bit is now complete.
2) A graceful stop, which was initiated by the setting of the
TCR[TFC_PAUSE] bit is now complete.
3) A graceful stop, which was initiated by the reception of a valid
full duplex flow control "pause" frame is now complete. Refer to
the "Full Duplex Flow Control" section of the Functional
Description chapter.
TXF
Transmit frame interrupt. This bit indicates that a frame has been
transmitted and that the last corresponding buffer descriptor has
been updated.
TXB
Transmit buffer interrupt. This bit indicates that a transmit buffer
descriptor has been updated.
RXF
Receive frame interrupt. This bit indicates that a frame has been
received and that the last corresponding buffer descriptor has been
updated.
RXB
Receive buffer interrupt. This bit indicates that a receive buffer
descriptor has been updated that was not the last in the frame.
MII
MII interrupt. This bit indicates that the MII has completed the data
transfer requested.
EBERR
Ethernet bus error. This bit indicates that a system bus error
occurred when a DMA transaction was underway. When the
EBERR bit is set, ECR[ETHER_EN] will be cleared, halting frame
processing by the FEC. When this occurs software will need to
insure that the FIFO controller and DMA are also soft reset.
LC
Late collison. This bit indicates that a collision occurred beyond the
collision window (slot time) in half duplex mode. The frame is
truncated with a bad CRC and the remainder of the frame is
discarded.
RL
Collision retry limit. This bit indicates that a collision occurred on
each of 16 successive attempts to transmit the frame. The frame is
discarded without being transmitted and transmission of the next
frame will commence. Can only occur in half duplex mode.
UN
Transmit FIFO underrun. This bit indicates that the transmit FIFO
became empty before the complete frame was transmitted. A bad
CRC is appended to the frame fragment and the remainder of the
frame is discarded.
—
Reserved, should be cleared.
Chapter 17. Fast Ethernet Controller (FEC)
Programming Model
Description
17-25
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