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Operation
therefore UBG1n = 0x00 and UBG2n = 0xD6.
23.5.1.2.2
External Clock
An external source clock (DTINn) can be used as is or divided by 16.
23.5.2 Transmitter and Receiver Operating Modes
Figure 23-19 is a functional block diagram of the transmitter and receiver showing the
command and operating registers, which are described generally in the following sections
and described in detail in Section 23.3, "Register Descriptions."
UART
Transmit Buffer
(UTBn)
(2 Registers)
UART Receive
Buffer (URBn)
(4 Registers)
Figure 23-19. Transmitter and Receiver Functional Diagram
23.5.2.1 Transmitter
The transmitter is enabled through the UART command register (UCRn). When it is ready
to accept a character, the UART sets USRn[TxRDY]. The transmitter converts parallel data
23-20
66MHz
Divider
=
----------------------------
=
215 decimal
[
]
32 x 9600
Externalclockfrequency
Baudrate
=
----------------------------------------------------------------
UARTn
UART Command Register (UCRn)
UART Mode Register 1 (UMR1n)
UART Mode Register 2 (UMR2n)
UART Status Register (USRn)
Transmitter Holding Register
Transmitter Shift Register
Receiver Holding Register 1
Receiver Holding Register 2
Receiver Holding Register 3
Receiver Shift Register
MCF5282 User's Manual
(
)
(
=
00D6 hexadecimal
[
] 16bitdivider
[
]
16or1
W
R/W
R/W
R
W
R
)
External
Interface
UTXD
FIFO
URXD
MOTOROLA
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