Motorola ColdFire MCF5281 User Manual page 781

Address
IPSBAR + 0x000
IPSBAR + 0x008
IPSBAR + 0x00C
IPSBAR + 0x010
IPSBAR + 0x011
IPSBAR + 0x012
IPSBAR + 0x013
IPSBAR + 0x014
IPSBAR + 0x01C
IPSBAR + 0x020
IPSBAR + 0x024
IPSBAR + 0x025
IPSBAR + 0x026
IPSBAR + 0x027
IPSBAR + 0x028
IPSBAR + 0x02A
IPSBAR + 0x02B
IPSBAR + 0x02C
IPSBAR + 0x02E
IPSBAR + 0x030
IPSBAR + 0x031
IPSBAR + 0x040
IPSBAR + 0x048
IPSBAR + 0x04C
IPSBAR + 0x050
IPSBAR + 0x054
IPSBAR + 0x080
IPSBAR + 0x084
IPSBAR + 0x08A
IPSBAR + 0x08C
IPSBAR + 0x092
IPSBAR + 0x094
MOTOROLA
Table A-3. Register Memory Map
Name
SCM Registers
Internal Peripheral System Base Address Register
Copy of RAMBAR
Reserved
Core Reset Status Register
Core Watchdog Control Register
Low-Power Interrupt Control Register
Core Watchdog Service Register
DMA Request Control Register
Bus Master Park Register
Master Privilege Register
Peripheral Access Control Register 0
Peripheral Access Control Register 1
Peripheral Access Control Register 2
Peripheral Access Control Register 3
Peripheral Access Control Register 4
Peripheral Access Control Register 5
Peripheral Access Control Register 6
Peripheral Access Control Register 7
Peripheral Access Control Register 8
Grouped Peripheral Access Control Register 0
Grouped Peripheral Access Control Register 1
SDRAMC Registers
DRAM Control Register
DRAM Address and Control Register 0
DRAM Mask Register Block 0
DRAM Address and Control Register 1
DRAM Mask Register Block 1
Chip Select Registers
Chip Select Address Register 0
Chip Select Mask Register 0
Chip Select Control Register 0
Chip Select Address Register 1
Chip Select Mask Register 1
Chip Select Control Register 1
Appendix A. Register Memory Map
Mnemonic Size
IPSBAR 32
RAMBAR 32
—
CRSR 8
CWCR 8
LPICR 8
CWSR 8
DMAREQC 32
MPARK 32
MPR 32
PACR0 8
PACR1 8
PACR2 8
PACR3 8
PACR4 8
PACR5 8
PACR6 8
PACR7 8
PACR8 8
GPACR0 8
GPACR1 8
DCR 16
DACR0 32
DMR0 32
DACR1 32
DMR1 32
CSAR0 16
CSMR0 32
CSCR0 16
CSAR1 16
CSMR1 32
CSCR1 16
A-3