Example Of A Misaligned Longword Transfer (32-Bit Port); Example Of A Misaligned Word Transfer (32-Bit Port) - Motorola ColdFire MCF5281 User Manual

misaligned at an odd address, and a longword is misaligned at an address not a multiple of
four. Although the MCF5282 enforces no alignment restrictions for data operands
(including program counter (PC) relative data addressing), additional bus cycles are
required for misaligned operands.
Instruction words and extension words (opcodes) must reside on word boundaries.
Attempting to prefetch a misaligned instruction word causes an address error exception.
The MCF5282 converts misaligned, cache-inhibited operand accesses to multiple aligned
accesses. Figure 13-19 shows the transfer of a longword operand from a byte address to a
32-bit port. In this example, SIZ[1:0] specify a byte transfer and a byte offset of 0x1. The
slave device supplies the byte and acknowledges the data transfer. When the MCF5282
starts the second cycle, SIZ[1:0] specify a word transfer with a byte offset of 0x2. The next
two bytes are transferred in this cycle. In the third cycle, byte 3 is transferred. The byte
offset is now 0x0, the port supplies the final byte, and the operation is complete.
31
Transfer 1
Transfer 2
Transfer 3
Figure 13-19. Example of a Misaligned Longword Transfer (32-Bit Port)
If an operand is cacheable and is misaligned across a cache-line boundary, both lines are
loaded into the cache. The example in Figure 13-20 differs from that in Figure 13-19 in that
the operand is word-sized and the transfer takes only two bus cycles.
31
Transfer 1
Transfer 2
Figure 13-20. Example of a Misaligned Word Transfer (32-Bit Port)
MOTOROLA
24 23
—
Byte 0
— —
—
Byte 3
24 23
— —
—
Byte 1
Chapter 13. External Interface Module (EIM)
16 15 8 7
—
Byte 1
—
16 15 8 7
—
—
Misaligned Operands
A[2:0]
0
—
001
Byte 2 010
—
100
A[2:0]
0
Byte 0 001
—
100
13-15