Source Address Registers (Sarn); Destination Address Registers (Darn) - Motorola ColdFire MCF5281 User Manual

DMA Controller Module Programming Model
16.4.1 Source Address Registers (SAR0–SAR3)
SARn, shown in Figure 16-4, contains the address from which the DMA controller requests
data.
31
Field
Reset
R/W
Address
The backdoor enable bit must be set in both the core and SCM
in order to enable backdoor accesses from the DMA to SRAM.
See
(RAMBAR)" for more details.
Flash accesses (reads/writes) by a bus master other than the
core (DMA controller or Fast Ethernet Controller), or writes to
Flash by the core during programming, must use the backdoor
Flash address of IPSBAR plus an offset of 0x0400_0000. For
example, for a DMA transfer from the first Flash location when
IPSBAR is still at its default location of 0x4000_0000, the
source register would be loaded with 0x4400_0000. Backdoor
Flash read accesses can be made with the bus master, but it
takes two cycles longer than a direct read of the Flash when
using the FLASHBAR address.
16.4.2 Destination Address Registers (DAR0–DAR3)
DARn, shown in Figure 16-5, holds the address to which the DMA controller sends data.
31
Field
Reset
R/W
Address
Figure 16-5. Destination Address Registers (DARn)
16-6
0000_0000_0000_0000_0000_0000_0000_0000
IPSBAR + 0x100, 0x140, 0x180, 0x1C0
Figure 16-4. Source Address Registers (SARn)
Section 8.4.2, "Memory
0000_0000_0000_0000_0000_0000_0000_0000
IPSBAR + 0x104, 0x144, 0x184, 0x1C4
MCF5282 User's Manual
SAR
R/W
NOTE
Base Address
NOTE
DAR
R/W
Register
MOTOROLA
0
0