Memory Map And Register Definition; Scm Register Map - Motorola ColdFire MCF5281 User Manual

Memory Map and Register Definition

— Core reset status register (CRSR) indicates type of last reset
— Core watchdog control register (CWCR) for watchdog timer control
— Core watchdog service register (CWSR) to service watchdog timer
• System bus master arbitration programming model (MPARK)
• System access control unit (SACU) programming model
— Master privilege register (MPR)
— Peripheral access control registers (PACRs)
— Grouped peripheral access control registers (GPACR0, GPACR1)
8.3 Memory Map and Register Definition
The memory map for the SCM registers is shown in Table 8-1. All the registers in the SCM
are memory-mapped as offsets within the 1 Gbyte IPS address space and accesses are
controlled to these registers by the control definitions programmed into the SACU.
IPSBAR
Offset
0x00_0000
0x00_0004
0x00_0008
0x00_000C
0x00_0010
0x00_0018
0x00_001C
0x00_0020
0x00_0024
0x00_0028
0x00_002c
0x00_0030
0x00_0034
0x00_0038
0x00_003C
1
The LPICR is described in Chapter 7, "Power Management."
8-2
Table 8-1. SCM Register Map
[31:24] [23:16]
CRSR CWCR
MPR
PACR0 PACR1
PACR4 —
PACR7 —
GPACR0 GPACR1
— —
— —
— —
MCF5282 User's Manual
[15:8]
IPSBAR
—
RAMBAR
—
1
LPICR
—
MPARK
—
PACR2
PACR5
PACR8
—
—
—
—
[7:0]
CWSR
PACR3
PACR6
—
—
—
—
—
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