Interrupt Mask Register (Eimr); Eimr Field Descriptions - Motorola ColdFire MCF5281 User Manual

Programming Model

17.5.4.2 Interrupt Mask Register (EIMR)

The EIMR register controls which interrupt events are allowed to generate actual interrupts.
All implemented bits in this CSR are read/write. This register is cleared upon a hardware
reset. If the corresponding bits in both the EIR and EIMR registers are set, the interrupt will
be signalled to the CPU. The interrupt signal will remain asserted until a 1 is written to the
EIR bit (write 1 to clear) or a 0 is written to the EIMR bit.
31 30
Field HBERR BABR BABT GRA TXF TXB RXF RXB
Reset
R/W
15
Field
Reset
R/W
Address
Bits
31–19
and Table 17-12.
18–0
17.5.4.3 Receive Descriptor Active Register (RDAR)
RDAR is a command register, written by the user, that indicates that the receive descriptor
ring has been updated (empty receive buffers have been produced by the driver with the
empty bit set).
Whenever the register is written, the RDAR bit is set. This is independent of the data
actually written by the user. When set, the FEC will poll the receive descriptor ring and
process receive frames (provided ECR[ETHER_EN] is also set). Once the FEC polls a
receive descriptor whose empty bit is not set, then the FEC will clear the RDAR bit and
cease receive descriptor ring polling until the user sets the bit again, signifying that
additional descriptors have been placed into the receive descriptor ring.
17-26
29 28 27
0000_0000_0000_0000
0000_0000_0000_0000
Figure 17-5. Interrupt Mask Register (EIMR)
Table 17-13. EIMR Field Descriptions
Name
See Figure 17-5 Interrupt mask. Each bit corresponds to an interrupt source defined
by the EIR register. The corresponding EIMR bit determines
whether an interrupt condition can generate an interrupt. At every
processor clock, the EIR samples the signal generated by the
interrupting source. The corresponding EIR bit reflects the state of
the interrupt signal even if the corresponding EIMR bit is set.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is not masked.
— Reserved, should be cleared.
MCF5282 User's Manual
26 25 24 23
MII EBERR LC
R/W
—
R/W
IPSBAR + 0x1008
Description
22 21 20 19 18
RL UN
MOTOROLA
16
—
0