Motorola ColdFire MCF5281 User Manual page 185

Table 7-7. CPU and Peripherals in Low-Power Modes (continued)
Module
Chip Configuration Module
Power Management
Clock Module
Edge port
Watchdog timer
Programmable Interrupt Timers
QADC
General Purpose Timers
FlexCAN
Flash Control Module
BDM
JTAG
1
"Program" Indicates that the peripheral function during the low-power mode is dependent on programmable bits in the
peripheral register map.
2
These modules can generate a interrupt which will exit a low-power mode. The CPU will begin to service the interrupt exception
after wakeup.
3
These modules can generate a reset which will exit any low-power mode.
4
The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any low-power mode. Upon exit
from halt mode, the previous low-power mode will be re-entered and changes made in halt mode will remain in effect.
MOTOROLA
Peripheral Status
Wait Mode
Enabled No
Enabled No
2
Enabled Yes
2
Enabled Yes
3
Program Yes
2
Enabled Yes
2
Enabled Yes
2
Enabled Yes
2
Enabled Yes
2
Enabled Yes
4
Enabled Yes
Enabled No
Chapter 7. Power Management
Functional Description
1
/ Wakeup Capability
Doze Mode
Enabled No Stopped
Enabled No Stopped
2
Enabled Yes Program
2
Enabled Yes Stopped
3
Program Yes Stopped
2
Program Yes Stopped
2
Program Yes Stopped
2
Enabled Yes Stopped
2
Enabled Yes Stopped
2
Enabled Yes Stopped
4
Enabled Yes Enabled
Enabled No Enabled
Stop Mode
No
No
2
Yes
2
Yes
No
No
No
No
No
No
4
Yes
No
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