Signals; Block Diagram; Memory Map And Registers; Watchdog Timer Block Diagram - Motorola ColdFire MCF5281 User Manual

Block Diagram

In halted mode with the WCR[HALTED] bit set, watchdog timer module operation stops.
In halted mode with the WCR[HALTED] bit cleared, the watchdog timer continues to
operate normally. When halted mode is exited, watchdog timer operation continues from
the state it was in before entering halted mode, but any updates made in halted mode
remain.
18.3 Block Diagram
System
Clock

18.4 Signals

The watchdog timer module has no off-chip signals.

18.5 Memory Map and Registers

This subsection describes the memory map and registers for the watchdog timer. The
watchdog timer has a IPSBAR offset for base address of 0x0014_0000.
18.5.1 Memory Map
Refer to Table 18-2 for an overview of the watchdog memory map.
18-2
16-bit WCNTR
Divide by
16-bit Watchdog Counter
8192
EN
WAIT
DOZE
HALTED
Figure 18-1. Watchdog Timer Block Diagram
MCF5282 User's Manual
IPBUS
16-bit WSR
Count = 0
Load Counter
16-bit WMR
IPBUS
Reset
MOTOROLA