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E
Electrical characteristics
bus
external output timing specifications, 33-11
processor input timing specifications, 33-10
ColdFire Flash module
module life characteristics, 33-10
program and erase characteristics, 33-9
DC specifications, 33-4
debug AC timing specifications, 33-27, 33-27
DMA timer AC timing specifications, 33-24
FEC AC timing specifications, 33-20
GPIO timing, 33-17
2
I
C input timing between SCL and SDA, 33-19
2
I
C input/output timing specifications, 33-19
2
I
C output timing between SCL and SDA, 33-20
JTAG and boundary scan timing, 33-25
maximum ratings, 33-1
MII async inputs signal timing, 33-22
MII receive signal timing, 33-21
MII serial management channel timing, 33-23
MII transmit signal timing, 33-21
PLL specifications, 33-6
QADC absolute maximum ratings, 33-7
QADC operating conversion specifications, 33-9
QADC operating electrical specifications, 33-7
QSPI AC timing specifications, 33-24
QSPI specifications, 33-24
reset and configuration override timing, 33-18
SDRAM timing, 33-16
thermal, 33-3
EMAC
data representation, 3-13
instruction set
execution times, 3-12
execution timing, 2-27
summary, 3-12
MAC, comparison, 3-1
memory map, 3-6
opcodes, 3-14
operation
fractional, 3-8
general, 3-3
programming model, 2-5
registers
BDM accesses, 29-33
mask (MASK), 3-11
status (MACSR), 3-6
ENABLE_TEST_CTRL instruction, 31-10
End-of-frame (EOF), 25-13
EPORT
low-power modes, 7-12, 11-1
memory map, 11-3
overview, 11-1
Index-4
INDEX
programming model, 7-1
registers
data direction (EPDDR), 11-4
flag (EPFR), 11-6
pin assignment (EPPAR), 11-4
pin data (EPPDR), 11-6
port data (EPDR), 11-5
port interrupt enable (EPIER), 11-5
Error counters, 25-15
Error interrupt (ERRINT) bit, 25-30
Ethernet
address recognition, 17-11
block diagram, 17-4
buffer descriptors
receive (RxBD), 17-47
driver/DMA operation, 17-46
collision handling, 17-17
electrical characteristics
MII receive signal timing, 33-21
MII serial management channel timing, 33-23
MII transmit signal timing, 33-21
error handling, 17-18
features, 17-1
frame reception, 17-10
frame transmission, 17-9
hash table
algorithm, 17-13
effectiveness, 17-14
initialization, 17-6
interface
10 Mbps 7-Wire, 17-3, 17-8
10 Mbps and 100 Mbps MII, 17-2, 17-8
interpacket gap time, 17-17
loopback, internal and external, 17-17
memory map
control/status registers, 17-20
MIB block counters, 17-21
operation
full duplex, 17-2, 17-16
half duplex, 17-2
low-power modes, 7-10
overview, 17-1
programming model, 17-20
reception errors
CRC, 17-19
frame length, 17-19
non-octet, 17-19
overrun, 17-19
truncation, 17-20
registers
control (ECR), 17-28
descriptor
descriptor
MCF5282 User's Manual
group
upper/lower
(GAUR/GALR), 17-39
individual
address
upper/lower
MOTOROLA
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