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Functional Description
frequency is six times the reference frequency. The presence of the MFD in the loop allows
the PLL to perform frequency multiplication, or synthesis.
In 1:1 PLL mode, the MFD is bypassed, and the effective multiplication factor is one.
9.7.4.5
PLL Lock Detection
The lock detect logic monitors the reference frequency and the PLL feedback frequency to
determine when frequency lock is achieved. Phase lock is inferred by the frequency
relationship, but is not guaranteed. The LOCK flag in the SYNSR reflects the PLL lock
status. A sticky lock flag, LOCKS, is also provided.
The lock detect function uses two counters. One is clocked by the reference and the other
is clocked by the PLL feedback. When the reference counter has counted N cycles, its count
is compared to that of the feedback counter. If the feedback counter has also counted N
cycles, the process is repeated for N + K counts. Then, if the two counters still match, the
lock criteria is relaxed by 1/2 and the system is notified that the PLL has achieved
frequency lock.
After lock is detected, the lock circuit continues to monitor the reference and feedback
frequencies using the alternate count and compare process. If the counters do not match at
any comparison time, then the LOCK flag is cleared to indicate that the PLL has lost lock.
At this point, the lock criteria is tightened and the lock detect process is repeated.
The alternate count sequences prevent false lock detects due to frequency aliasing while the
PLL tries to lock. Alternating between tight and relaxed lock criteria prevents the lock
detect function from randomly toggling between locked and non-locked status due to phase
sensitivities. Figure 9-6 shows the sequence for detecting locked and non-locked
conditions.
In external clock mode, the PLL is disabled and cannot lock.
9-14
MCF5282 User's Manual
MOTOROLA
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