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Table 26-2. MCF5282 Ports Module Memory Map (continued)
IPSBAR +
31–24
Offset
0x10_0014
DDRA
0x10_0018
DDRE
0x10_001C
DDRJ
0x10_0020
DDRAS
0x10_0024
DDRTD
0x10_0028
PORTAP/SETA
0x10_002C
PORTEP/SETE
0x10_0030
PORTJP/SETJ
0x10_0034
PORTASP/SETAS
0x10_0038
PORTTDP/SETTD
0x10_003C
CLRA
0x10_0040
CLRE
0x10_0044
CLRJ
0x10_0048
CLRAS
0x10_004C
CLRTD
0x10_0050
PBCDPAR
0x10_0054
PJPAR
0x10_0058
PEHLPAR
0x10_005C
PUAPAR
0x10_0060–
$007C
1
S/U = supervisor or user mode access. User mode accesses to supervisor-only addresses have no effect and cause a cycle termination transfer
error.
2
Writing to reserved address locations has no effect and reading returns 0s.
MOTOROLA
23–16
Port Data Direction Registers
DDRB
DDRF
DDRDD
DDRQS
DDRUA
Port Pin Data/Set Data Registers
PORTBP/SETB
PORTFP/SETF
PORTDDP/SETDD
PORTQSP/SETQS
PORTUAP/SETUA
Port Clear Output Data Registers
CLRB
CLRF
CLRDD
CLRQS
CLRUA
Port Pin Assignment Registers
PFPAR
PSDPAR
PQSPAR
Reserved
Chapter 26. General Purpose I/O Module
Memory Map/Register Definition
15–8
DDRC
DDRG
DDREH
DDRSD
2
Reserved
PORTCP/SETC
PORTGP/SETG
PORTEHP/SETEH
PORTSDP/SETSD
2
Reserved
CLRC
CLRG
CLREH
CLRSD
2
Reserved
PEPAR
PASPAR
PTCPAR
2
Reserved
2
7–0
Access
DDRD
S/U
DDRH
S/U
DDREL
S/U
DDRTC
S/U
S/U
PORTDP/SETD
S/U
PORTHP/SETH
S/U
PORTELP/SETEL
S/U
PORTTCP/SETTC
S/U
S/U
CLRD
S/U
CLRH
S/U
CLREL
S/U
CLRTC
S/U
S/U
S/U
S/U
PTDPAR
S/U
S/U
26-7
1
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