Table of Contents
Advertisement
control (I2CR), 24-8
data I/O (I2DR), 24-10
frequency divider (I2FDR), 24-7
status (I2SR), 24-9
software response, 24-11
START generation, 24-11
STOP generation, 24-12
system configuration, 24-3
timing diagrams
input/output timing, 33-20
IDCODE instruction, 31-9
Identifier (ID) bits, 25-7
IDLE bit, 25-29
Illegal instruction exception, 2-14
Information processing time (IPT), 25-14
Input capture, 20-17
Instructions
additions, 2-9
enhancements
BITREV, 2-29
BYTEREV, 2-30
FF1, 2-31
STRLDSR, 2-32
execution timing
branch, 2-28
EMAC, 2-27
miscellaneous, 2-26
MOVE, 2-22
one-operand, 2-24
two-operand, 2-24
JTAG
BYPASS, 31-11
CLAMP, 31-11
ENABLE_TEST_CTRL, 31-10
EXTEST, 31-9
HIGHZ, 31-10
IDCODE, 31-9
LOCKOUT_RECOVERY, 31-10
SAMPLE/PRELOAD, 31-9
TEST_LEAKAGE, 31-10
RTE, 2-16
Intermission, 25-13
Interrupt controller
features, 10-1
interrupts
ColdFire Flash module, 6-25
debug, 2-15, 29-38
FlexCAN, 25-19
overview, 10-1
prioritization, 10-3
priority mask (I) bit, 2-7
programmable interrupt timers, 19-8
QADC
operation, 27-75
sources, 27-76
MOTOROLA
INDEX
recognition, 10-3
sources, 10-12
vector determination, 10-4
memory map, 10-5
operation
general, 10-3
low-power modes, 7-10
registers
(IACKLPRn), 10-11
interrupt control (ICRnx), 10-11
interrupt
interrupt pending high/low (IPRHn, IPRLn), 10-6
interrupt request level (IRLRn), 10-10
mask high/low (IMRHn, n), 10-8
Interrupt-acknowledge (IACK), 2-10
J
JTAG
block diagram, 31-2
electrical characteristics
boundary scan timing, 33-25
features, 31-2
initialization, 31-11
nonscan chain operation, 31-12
restrictions, 31-11
instructions
BYPASS, 31-11
CLAMP, 31-11
ENABLE_TEST_CTRL, 31-10
EXTEST, 31-9
HIGHZ, 31-10
IDCODE, 31-9
LOCKOUT_RECOVERY, 31-10
SAMPLE/PRELOAD, 31-9
TEST_LEAKAGE, 31-10
low-power modes, 7-16
memory map, 31-5
overview, 31-1
registers
boundary scan, 31-6
bypass, 31-6
IDCODE, 31-5
instruction shift (IR), 31-5
JTAG_CFM_CLKDIV, 31-6
TEST_CTRL, 31-6
TAP controller, 31-7
timing diagrams
BKPT timing, 33-27
boundary scan, 33-26
test access port, 33-26
test clock input, 33-25
TRST timing, 33-26
MCF5282 User's Manual
force
high/low
INTFRCLn), 10-9
(INTFRCHn,
Index-7
Advertisement
Table of Contents
