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Programming Model
In order to keep the chip selects asserted for all transfers, the
QWR[CSIV] bit must be set to control the level that the chip
selects return to after the first transfer.
QSPICS[3:0]
QS1
QSPI_CLK
QSPI_DOUT
QSPI_DIN
QS1: QSPICS to QSPI_CLK
QS2: QSPI_CLK to QSPI_DOUT VALID
QS3: QSPI_CLK to QSPI_DOUT HOLD
QS4: QSPI_DIN to QSPI_CLK SETUP
QS5: QSPI_DIN to QSPI_CLK HOLD
1 T1 is defined as the clock period in ns.
22.5.8 Programming Example
The following steps are necessary to set up the QSPI 12-bit data transfers and a QSPI_CLK
of 4.125 MHz. The QSPI RAM is set up for a queue of 16 transfers. All four QSPI_CS
signals are used in this example.
1. Write the QMR with 0xB308 to set up 12-bit data words with the data shifted on the
falling clock edge, and a QSPI_CLK frequency of 4.125 MHz (assuming a 66-MHz
system clock).
2. Write QDLYR with the desired delays.
22-16
NOTE
QS2
QS3
Min
1T1
0 ns
10 ns
10 ns
Figure 22-11. QSPI Timing
MCF5282 User's Manual
QS5
QS4
Max
20 ns
MOTOROLA
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