Table of Contents
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Format error exception, 2-16
Format value, 2-16
Frame length violation, Ethernet, 17-19
Frame reception, FlexCAN, 25-9
Frame transmission, FlexCAN, 25-9
G
General purpose timers
block diagram, 20-2
features, 20-1
functional description, 20-17
GPIO ports, 20-19
input capture, 20-17
interrupts
channel flags, 20-22
pulse accumulator input, 20-22
pulse accumulator overflow, 20-22
timer overflow, 20-22
low-power modes, 7-13
memory map, 20-4
operation
event counter mode, 20-18
gated time accumulation mode, 20-19
low-power modes, 20-3
output compare, 20-17
prescaler, 20-17
pulse accumulator
event counter mode, 20-18
gated time accumulation, 20-19
registers
channel (GPTCn), 20-13
compare force (GPCFORC), 20-6
control 1–2 (GPTCTLn), 20-9
counter (GPTCNT), 20-7
flag 1–2 (GPTFLGn), 20-12
input
capture/output
(GPTIOS), 20-5
interrupt enable (GPTIE), 20-10
output compare 3 data (GPTOC3D), 20-7
output compare 3 mask (GPTOC3M), 20-6
port data (PORTTn), 20-16
port data direction (GPTDDR), 20-16
pulse accumulator control (GPTPACTL), 20-13
pulse accumulator counter (GPTPACNT), 20-15
pulse accumulator flag (GPTPAFLG), 20-14
system control 1–2 (GPTSCRn), 20-8, 20-11
toggle-on-overflow (GPTTOV), 20-9
reset, 20-21
GPIO
block diagram, 26-2
electrical characteristics
timing, 33-17
features, 26-3
initialization, 26-26
Index-6
INDEX
compare
select
MCF5282 User's Manual
memory map, 26-6
operation, 26-3
low-power modes, 7-10
overview, 26-1, 26-3
registers
port AS pin assignment (PASPAR), 26-19
port B/C/D pin assignment (PBCDPAR), 26-14
port clear output data (CLRn), 26-12
port data direction (DDRn), 26-9
port E pin assignment (PEPAR), 26-15
port EH/EL pin assignment (PEHLPAR), 26-20
port F pin assignment (PFPAR), 26-17
port J pin assignment (PJPAR), 26-18
port output data (PORTn), 26-8
port pin data/set data (PORTnP/SETn), 26-11
port QS pin assignment (PQSPAR), 26-21
port SD pin assignment (PSDPAR), 26-19
port TC pin assignment (PTCPAR), 26-22
port TD pin assignment (PTDPAR), 26-23
port UA pin assignment (PUAPAR), 26-24
timing diagrams, 33-18
digital input, 26-25
digital output, 26-26
H
Halt, fault-on-fault, 29-17
Hash table
algorithm, 17-13
effectiveness, 17-14
HIGHZ instruction, 31-10
I
2
I
C
arbitration procedure, 24-4
clock
stretching, 24-5
synchronization, 24-5
electrical characteristics
input timing between SCL and SDA, 33-19
output timing between SCL and SDA, 33-20
features, 24-1
handshaking, 24-5
lost arbitration, 24-14
operation
low-power modes, 7-9
slave mode, 24-13
overview, 24-1
programming
examples, 24-10
model, 24-6
protocol, 24-3
registers
address (I2ADR), 24-6
MOTOROLA
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