Table of Contents
Advertisement
26.3.2.3 Port Pin Data/Set Data Registers (PORTnP/SETn)
The PORTnP/SETn registers reflect the current pin states and control the setting of output
pins when the pin is configured for digital I/O.
Most PORTn registers have a full 8-bit implementation, as shown in Figure 26-10. The
remaining PORTn registers use fewer than eight bits. Their bit definitions are shown in
Figure 26-11, Figure 26-12, and Figure 26-13.
The PORTnP/SETn registers are read/write. At reset, the bits in the PORTnP/SETn
registers are set to the current pin states.
Reading a PORTnP/SETn register returns the current state of the port n pins.
Setting a PORTnP/SETn register sets the corresponding bits in the PORTn register. Writing
0s has no effect.
7
Field
PORTnP7/
SETn7
Reset
R/W:
Address
IPSBAR + 0x10_0028 (PORTAP/SETA), 0x10_0029 (PORTBP/SETB), 0x10_002A (PORTCP/SETC),
0x10_002B (PORTDP/SETD), 0x10_002C (PORTEP/SETE), 0x10_002D (PORTFP/SETF), 0x10_002E
(PORTGP/SETG), 0x10_002F (PORTHP/SETH), 0x10_0030 (PORTJP/SETJ), 0x10_0031
(PORTDDP/SETDD), 0x10_0032 (PORTEHP/SETEH), 0x10_0033 (PORTELP/SETEL)
Figure 26-10. Port Pin Data/Set Data Registers (8-bit)
7
Field
—
PORTnP6/SE
Tn6
Reset
0
R/W:
—
Address
Figure 26-11. Port Pin Data/Set Data Register (7-bit)
7
Field
—
Reset
00
R/W:
—
Address
Figure 26-12. Port Pin Data/Set Data Registers (6-bit)
MOTOROLA
6
5
PORTnP6/
PORTnP5/
SETn6
SETn5
6
5
PORTnP5/SE
PORTnP4/SE
Tn5
IPSBAR + 0x10_0035 (PORTQSP/SETQS)
6
5
PORTnP5/
PORTnP4/
SETn5
IPSBAR + 0x10_0034 (PORTASP/SETAS), 0x10_0036 (PORTSDP/SETSD)
Chapter 26. General Purpose I/O Module
4
3
PORTnP4/
PORTnP3/
PORTnP2/
SETn4
SETn3
Current Pin State
R/W
4
3
PORTnP3/SE
PORTnP2/SE
Tn4
Tn3
Current Pin State
R/W
4
3
PORTnP3/
PORTnP2/
SETn4
SETn3
SETn2
Current Pin State
R/W
Memory Map/Register Definition
2
1
PORTnP1/
PORTnP0/
SETn2
SETn1
SETn0
2
1
PORTnP1/SE
PORTnP0/SE
Tn2
Tn1
2
1
0
PORTnP1/
PORTnP0/
SETn1
SETn0
0
0
Tn0
26-11
Advertisement
Table of Contents
