Peripheral Access Control Register (Pacrn); Pacr Field Descriptions; Pacr Accessctrl Bit Encodings; Peripheral Access Control Registers (Pacrs) - Motorola ColdFire MCF5281 User Manual

modules only support operand reads and writes. Each PACR follows the format illustrated
in Figure 8-9. For a list of PACRs and the modules that they control, refer to Table 8-12.
7
Field LOCK1
Reset
R/W
Address
Figure 8-9. Peripheral Access Control Register (PACRn)
Bits Name
7 LOCK1
6–4 ACCESS_CTRL1 This 3-bit field defines the access control for the given platform peripheral.
3 LOCK0
2–0 ACCESS_CTRL0 This 3-bit field defines the access control for the given platform peripheral.
Table 8-11. PACR ACCESSCTRL Bit Encodings
Table 8-12. Peripheral Access Control Registers (PACRs)
IPSBAR Offset
0x024
0x025
0x026
MOTOROLA
6
ACCESS_CTRL1
IPSBAR + 0x24 + Offset
Table 8-10. PACR Field Descriptions
This bit, when set, prevents subsequent writes to ACCESSCTRL1. Any attempted
write to the PACR generates an error termination and the contents of the register are
not affected. Only a system reset clears this flag.
The encodings for this field are shown in Table 8-11.
This bit, when set, prevents subsequent writes to ACCESSCTRL0. Any attempted
write to the PACR generates an error termination and the contents of the register are
not affected. Only a system reset clears this flag.
The encodings for this field are shown in Table 8-11.
Bits Supervisor Mode
000 Read/Write
001 Read
010 Read
011 Read
100 Read/Write
101 Read/Write
110 Read/Write
111 No Access
Name
PACR0
PACR1
PACR2
Chapter 8. System Control Module (SCM)
System Access Control Unit (SACU)
4 3 2
LOCK0
0000_0000
R/W
Description
User Mode
No Access
No Access
Read
No Access
Read/Write
Read
Read/Write
No Access
Modules Controlled
ACCESS_CTRL1
SCM
EIM
UART0
0
ACCESS_CTRL0
ACCESS_CTRL0
SDRAMC
DMA
UART1
8-17