Paragraph
Number
14.2
14.2.1
External Interface Module (EIM) Signals .................................................. 14-18
14.2.2
SDRAM Controller Signals ........................................................................ 14-21
14.2.3
14.2.4
14.2.5
14.2.6
14.2.7
Queued Serial Peripheral Interface (QSPI) Signals.................................... 14-25
14.2.8
FlexCAN Signals ........................................................................................ 14-26
2
14.2.9
I
C Signals .................................................................................................. 14-26
14.2.10
UART Module Signals ............................................................................... 14-26
14.2.11
14.2.12
DMA Timer Signals.................................................................................... 14-28
14.2.13
14.2.14
Debug Support Signals ............................................................................... 14-30
14.2.15
Test Signals................................................................................................. 14-32
14.2.16
15.1
Overview........................................................................................................... 15-1
15.1.1
Definitions .................................................................................................... 15-1
15.1.2
Block Diagram and Major Components ....................................................... 15-2
15.2
15.2.1
15.2.2
Memory Map for SDRAMC Registers......................................................... 15-4
15.2.3
15.2.4
Initialization Sequence................................................................................ 15-17
15.3
SDRAM Example ........................................................................................... 15-19
15.3.1
15.3.2
DCR Initialization....................................................................................... 15-20
15.3.3
DACR Initialization.................................................................................... 15-21
15.3.4
DMR Initialization...................................................................................... 15-22
15.3.5
Mode Register Initialization ....................................................................... 15-23
15.3.6
Initialization Code....................................................................................... 15-24
16.1
Overview........................................................................................................... 16-1
16.1.1
DMA Module Features ................................................................................. 16-2
MOTOROLA
CONTENTS
Title
Chapter 15
Synchronous DRAM Controller Module
Chapter 16
DMA Controller Module
Contents
Page
Number
xi